can change the delay of the AD9739 output

Hi Licunxu,

I appreciate you asking, and I'd want to elaborate on how I understand AD9744. The output propagation delay, or Tpd, is 1ns Typ. You don't seem to have any direct influence on it, and it's relative to the rising edge of the clock. However, you can alter the rising edge of the clock in relation to the external data availability to regulate the setup time (Ts) and improve timing.

While AD9739 includes a delay lock loop (DLL) circuit controlled via a mu controller to optimize the timing hand-off between the AD9739 digital clock domain and TxDAC core. Besides ensuring proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing alignment over temperature, time, and power supply variation. This will save you the effort of trying to adjust the clock delay relative to the data.

The THEORY OF OPERATION section in AD9739 should be carefully reviewed because there have been significant changes made to the data ports (DB0/DB1) and the clock timing since AD9744.

I hope this clarifies your query; if not, let me know if you have any other inquiries.

Regards

Adam