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Category: Hardware

hi all:
I'm a beginner in DACs.I have a question in AD9136.
In the example of AD9136 rev.D P79. As shown below.
We can known SERDES lanes run at 7.3728 Gbps.

(1)And the fref of SERDES PLL is 1/40 of the lane rate. That is 184.32MHz. As shown below in P37.

(2)In P38, the fref is equal to BIT RATE÷40. And we can get the fref from the equations in P37. ByteRate is 184.32MHz. And BIT RATE is 23.04MHz. So the fref is 0.576MHz. (I think the BIT RATE is ByteRate?)

(3)In P4, the fref of SERDES PLL is DACCLK.But DACCLK is 1474.56MHz in the above example. Is there some correlation between fref and DACCLK?

So,I'm confused about fref of SERDES PLL. And Which of the above is correct?

Best Regards

Parents
• Hi xiaohexiang,

fREF term is used to refer to the frequency of the REFCLK fed into CLK+/- differential pins (pins 2 and 3). DACCLK is equal to fREF if DACCLK is sourced directly from CLK+/- (pins 2 and 3). If the DAC PLL is employed, the DACCLK is a multiple of fREF. The DACCLK is used to generate all internal clocks required by the DAC.

Regards,

Shine

But fREF term also seems to mean the reference of serdes pll. And I want to known the ralationship between the reference of serdes pll and DACCLK?

• Hi  ,

Apologies for the delay. The relationship between fRef and DACCLK is indicated in Equation 2 in page 73 of the Rev D datasheet. As mentioned by ShineC above, the DACCLK is a multiple of fREF through clock multiplication, and DACCLK will be used to generate the internal clocks of the DAC, including the SERDES PLL.

Regards,

Marco