I'm a little confused about the datasheet for the LTC1666/7/8 and how fast I can update the DAC. On page 4, it lists the min clock high time (TCLKH) as 5ns and min clock low time (TCLKL) as 8ns. I would think that that would mean I can input a clock that is high for 5ns and low for 8ns into the LTC1666 and that would be ok. But this clock would be at a data rate of 1/13ns or 76.9 Msps and the same table says the minimum value for the max clock / update rate is 50 Msps. Does this mean the TCLKH must be 5ns (or greater) and TCLKL must be 8ns (or greater) but also that TCLKH + TCLKL must equal 20ns (or greater) to be within specifications? Or is there a way to run the clock at 76.9Msps but not update the DAC every time to somehow maintain the 50Msps requirement? Also, the parts put 75 Msps are typical... does this mean that some (most) devices will work at 75 Msps but some will not? And to guarantee properly getting data in to the device and updating the output, the data rate must be 50 Msps?
Thank you,
