Question on how to synchronize DAC outputs when using two AD9176s

Question

Two AD9176s connected to one XLINX FPGA. 
 Both XILINX and two DACs are supplied with DCLK and SYSREF through the same Clock IC. 
 It receives SYNC signals from two DACs and receives SYNC input from JESD204 IP inside XILNX. 
 The same data pattern is being transmitted at the same time, but when measuring the DAC output with an oscilloscope, the output skew occurs about 2-20ns every time the power is turned off-on. 
 Is there a way to align between the two DAC outputs?

kberry · Accepted Answer

Hi Justin, 
 Have you reviewed the Sync Procedure section for subclass 1 in the datasheet, pgs 42-45? In order to achieve deterministic latency such that both chips transmit at the same time after each power cycle the 9176s must be set up in subclass 1 (set 0x458[7:5]=1). In this mode the internal timing alignment of the chip is triggered by the incoming sysref signal. The Link Delay section explains how delay can be added such that the ILAS-to-data transition always happens within the same LMFC cycle on both chips. If there is an offset between the arrival of the sysref signal to each chip due to layout additional delay can be added internally.)

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Question on how to synchronize DAC outputs when using two AD9176s