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DAC

Category: Software
Product Number: AD9136_FMC_EBZ
Software Version: ACE
Hi, thank you very much for your help! Now I can successfully read and write registers including ad9136 and ad9516 using verilog. 
But I ran into a new trouble. I'm confused about the Fin parameter in the Initial Configuration Summary interface in ACE software, I don't know what input it refers to?
I already know that RefClk corresponds to the input CLK of the PLL, and FDAC is the final target output frequency of the DAC. This bothers me a lot.
The ad9516 should output two kinds of clocks to the ad9136, one is input to the phase-locked loop, and the other is SYSRef, but it seems that SYSREF is not needed here.
I want to export register list in ACE software, how should I set these parameters to get the correct register list?
Parents
  • Can anyone help me, there are too few documents available for this board, I see the ADCLK925 chip on the schematic as a clock buffer. I input the 250M clock of LVCMOS_18, but the chip seems to have no output. Is there any specification on what standard the input clock should be. I only see that D to D_N is rated at ±1.8V in the manual.

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  • Can anyone help me, there are too few documents available for this board, I see the ADCLK925 chip on the schematic as a clock buffer. I input the 250M clock of LVCMOS_18, but the chip seems to have no output. Is there any specification on what standard the input clock should be. I only see that D to D_N is rated at ±1.8V in the manual.

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