DAC

Does Fin refer to the input clock of ad9516? 
Currently I am using verilog configuration registers on vivado, but it is a bit cumbersome.
 ACE software can use the computer to configure the registers, and use xilinx FPGA jesd204B to send data to the DAC. 
Is this feasible?

Can anyone help me, there are too few documents available for this board, I see the ADCLK925 chip on the schematic as a clock buffer. I input the 250M clock of LVCMOS_18, but the chip seems to have no output. Is there any specification on what standard the input clock should be. I only see that D to D_N is rated at ±1.8V in the manual.

Now I use an RS SMB100A signal generator to solve the problem. Output 250M sine wave of 3dbm, which solves the problem. The reason why I didn't see the waveform before is that the bandwidth of the oscilloscope is limited. I switched to a spectrum analyzer and saw the frequency domain information correctly. The problem now is that I get the register list according to the evaluation software setting of ad9516-1, use the clock distribution mode, configure the registers correctly but do not get the desired output signal, what is the possible reason? I confirmed that all the registers I have exported are the registers I entered, except the one whose address is 0x002 reads 0x040, and I set it to 0x010, but its description is reserved, what is the meaning of this? Can you help me?ShineC 

Hi user10724 ,

Please confirm if I understand your question correctly - you are having problems on the AD9516 clock buffer?
If yes, might be good to post a question in Clock and Timing 

Regards,

Shine

Thank you very much for your reply, I have already solved it, it is the register list generated by the evaluation software, the last register 0x232 address software generated is 0x00, actually set it to 0x01, it activates all registers. I'm going to debug jesd204 recently, but I don't feel it will go well.