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Can I get a deterministic phase on the AD9171 by triggering an NCO reset with the sysref signal?

Category: Datasheet/Specs
Product Number: AD9171

Hi all,

Due to the design needs, I need the AD9171 to output pulse signals at non-equal intervals, but after testing, I found that the initial phase of the pulses output by the AD9171 is not the same when ad9171 input baseband is same.

Since the output signal is obtained after mixing inside the AD9171 I guess the NCO is causing the problem.

According to the datasheet, I think I can reset the NCO by sending a sysref signal after the 204B subclass1 link is established to ensure that the initial phase of each pulse output from the AD9171 is the same. But the datasheet does not explain NCO reset in detail.

So I have the following questions:

1.After the AD9171 receives the sysref signal to reset the NCO, how long does it take for the NCO to operate properly?

2.To get the deterministic phase, can I use the FPGA to generate sysref signals to provide to the AD9171 and ADI 204B IP?

Any answer would be helpful, thanks.

  • Hello,

    The latency between sysref sensing and NCO reset is dependent on the configuration of the device. In order to reset the NCO with the sysref signal 0x113 should be cleared to 0x00 for both main dacs (otherwise the FTW load acknowlegement bit is high, and no NCO updates will take place). Then the device needs to be "armed" for the arrival of the sysref pulse, by toggling bit 0x11e[7] low to high. This bit is not in the current register map. If you are in single link mode make sure 0x112[0] = 0 for dac 1, and make sure you are paging dac0 when you toggle 0x11e[7] for arming. The NCO should reset to phase 0, but if you need a different phase you can update the phase_offset registers (0x11C/D). Once this is working you can measure the latency from the sysref pulse to the phase reset on the output for your configuration.

    If you are just using sysref to reset the NCOs (i.e. not to do a oneshot sync and align the jesd clocks on the 9171 and the FPGA or the JTx device) then you can send the signal from the FPGA, but if you are using sysref for deterministic latency on your jesd link(s) (i.e. to ensure that chip data transmission begins at the same time from power cycle to power cycle) then you need to send a synchronous sysref signal to both the 9171 and the FPGA, so you would want to use an external clock distribution chip or two reference locked sources for that.