Can I get a deterministic phase on the AD9171 by triggering an NCO reset with the sysref signal?

Hello,

The latency between sysref sensing and NCO reset is dependent on the configuration of the device. In order to reset the NCO with the sysref signal 0x113 should be cleared to 0x00 for both main dacs (otherwise the FTW load acknowlegement bit is high, and no NCO updates will take place). Then the device needs to be "armed" for the arrival of the sysref pulse, by toggling bit 0x11e[7] low to high. This bit is not in the current register map. If you are in single link mode make sure 0x112[0] = 0 for dac 1, and make sure you are paging dac0 when you toggle 0x11e[7] for arming. The NCO should reset to phase 0, but if you need a different phase you can update the phase_offset registers (0x11C/D). Once this is working you can measure the latency from the sysref pulse to the phase reset on the output for your configuration.

If you are just using sysref to reset the NCOs (i.e. not to do a oneshot sync and align the jesd clocks on the 9171 and the FPGA or the JTx device) then you can send the signal from the FPGA, but if you are using sysref for deterministic latency on your jesd link(s) (i.e. to ensure that chip data transmission begins at the same time from power cycle to power cycle) then you need to send a synchronous sysref signal to both the 9171 and the FPGA, so you would want to use an external clock distribution chip or two reference locked sources for that.