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Placement of AD9117 FSADJ pin resistor and capacitor

Category: Hardware
Product Number: AD9117


I have a question about the location of the resistor and capacitor to be placed on the FSADJ pin of the AD9117.

Datasheet P45 describes the Rset resistor connected to FSADJ.
Here, when mounting 4kΩ or more, it is described to divide the resistance into 4kΩ + 12kΩ and add a 1μF capacitor from 4kΩ to Ground.

Is the recognition correct with the configuration shown below?
If I'm wrong, please let me know the correct configuration.

I would appreciate it if you could reply.

Best Regards,

Top Replies

  • Hi Knj,


    The configuration should be similar to the schematic found in page 5 of AD9117 Eval-board schematic (IOUT Network and FSADJ1). Under the jumper JP12, the 12kΩ resistor can be directly connected to GND, and on the other branch is the 4kΩ resistor and the capacitor. This is so that there's will still be a DC path for the FSADJ current to GND. 


    Note that this configuration isn't required for a resistance greater than 4kΩ. You can still connect a resistance up to 16kΩ directly to FSADJ pin without splitting it into 4kΩ plus the additional resistance. The configuration is just helpful for the adjustment span of IxOUTFS and certain applications such as small signal multiplying applications.


    Warm regards,



  • Hi, Marco

    Thank you for your reply.
    I checked the circuit diagram of the evaluation board, and 12kΩ and 4kΩ are connected in parallel.
    Will a current equivalent to Rset = 16kΩ flow in this configuration?

    Also, the datasheet recommends 1uF for the additional capacitor, but the schematic for the evaluation board is 10pF.
    Which do you prefer?

    I would appreciate it if you could reply.

    Best Regards,