Post Go back to editing

AD9117 DAC Reset Issue

Category: Hardware
Product Number: AD9117

Dear team,

We are facing DAC reset issue on AD9117(DAC)

During power on time DAC registers randomly jump to 0,FF & 0,A instead of default values.

For odd registers the value read is "0" and for even registers the value read is "FF" during first reading.

During Second time reading "0" is read for odd registers and "A" is read for even registers.

Read the registers, after writing the corresponding values in corresponding registers still the junk values only read (the write values didn't write properly).

The reset pulse given for DAC reset pin is 500us for every power ON.

The DAC register write operation is starts after 13ms from DAC reset.

Note: The above mentioned issues are happened only random power On not frequently.

with regards,
Arumuga Raj S
System Engineer
Datapatterns(India)Ltd.



Also share the SPI timing diagram
[edited by: Arumugam2608 at 3:45 AM (GMT -5) on 10 Feb 2023]

Top Replies

  • Hi  ,

    500us reset pulse should be enough duration to reset the registers to their default values, but can you check if you providing the right reset pulse to the RESET/PINMD (pin 35)? The pulse…

Parents
  • Hi  ,

    500us reset pulse should be enough duration to reset the registers to their default values, but can you check if you providing the right reset pulse to the RESET/PINMD (pin 35)? The pulse will depend which mode you are in: SPI mode or PIN mode. Please refer to page 52 of the AD9117 datasheet

    Also, are you using the AD9117 evaluation board? If not, can we get a copy of your board schematic? Just so we could check if your power supply (AVDD, CVDD, DVDDIO, DVDD) are within operating conditions, as well as the DAC connections. 

  • Hi JMMina,

    Herewith, I have attached the DAC power supply vs reset pulse images,please provide suggestion.

    Also, Provide the SPI timing diagram. This will help us for further analysis.

    Thanks&Regards,

    Arumuga Raj S

  • Hi  :

     

    Apologies for the delayed response. SPI timing diagram can be found in page 35 of the datasheet. For the pulse images, can you provide the full length of the RESET pulse (green trace)? Pin 35 must be pulled low to DVSS to choose SPI mode, afterwards you provide the pulse width of 50 ns (minimum) to reset the SPI registers to their default values. In your case, please ensure that you set the pin low again after the 500us reset pulse.

     

    Can you provide the register addresses/values that you are reading? They should follow the default SPI register values indicated at page 36 of the datasheet.

    Regards,

    Marco

  • Hi JMMina,

    We need SPI Write and Read timing diagram,In datasheet mentioned as write and read sequence.

    Initially we are given to 500us reset pulse. At that time
    DAC register randomly jump to junk values(odd registers 0x0A & 0xFF, even registers 0).

    We followed below mentioned sequence

    Still DAC registers jump to Junk values(randomly).

    Please provide the valuable solution.

    Thanks&Regards,

    Arumuga Raj S

Reply
  • Hi JMMina,

    We need SPI Write and Read timing diagram,In datasheet mentioned as write and read sequence.

    Initially we are given to 500us reset pulse. At that time
    DAC register randomly jump to junk values(odd registers 0x0A & 0xFF, even registers 0).

    We followed below mentioned sequence

    Still DAC registers jump to Junk values(randomly).

    Please provide the valuable solution.

    Thanks&Regards,

    Arumuga Raj S

Children