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AD9106 - Trigger Pattern Stop

Category: Software
Product Number: AD9106
Software Version: N/A

Hello!

I am using a custom made board with AD9106 which is controlled by an external microcontroller. 

I am currently uploading a waveform into the SRAM of the AD9106 and the toggling the Trigger pin to start the pattern. I want to be able to define the start and stop of every pattern by toggling the Trigger pin low or high.

The 'start' part works just fine, but I cannot terminate the pattern early, as shown in Figure 44 of the Datasheet or as explained here: "The rising edge on the trigger terminal is a request for the termination of pattern generation (see Figure 44). ". 

The pattern will finish running with the value set in the "PAT_PERIOD" register, it will not stop even if Trigger is high. Is there a bit that I need to set to be able to stop the pattern early? Or stopping early is not possible if generating pattern from RAM, only with predefined patterns?

Thank you! Let me know if you need any more information

-Cezar

Top Replies

  • Hi  , 

     

    What is your DAC clock frequency? When triggering high, the pattern generation will not stop instantaneously. There would be a delay between the rising edge of the trigger and the pattern…

  • Here is an example: 

    I'm not sure what is happening with the start/stop here. 

    The start address is 0, stop address is 4095 and PAT_PERIOD is set to 1000. However, the waveform period is 13.76us, as can be seen in waveform above. 

  • Hi  , 

     

    What is your DAC clock frequency? When triggering high, the pattern generation will not stop instantaneously. There would be a delay between the rising edge of the trigger and the pattern generation OFF, similar to the falling edge of the trigger and pattern generation ON when starting a pattern. This delay is a measure of the number of clock cycles following the trigger -- which will depend on your DAC clock frequency.  For the maximum sampling rate (180Msps), the minimum setup time is 1.5 ns, and the minimum hold time is 2.0 ns. Please refer to Table 3 in Page 7 of the datasheet.

     

    Also, what is your expected waveform period? The 13.76us for the 4096 addresses of the RAM results to a sampling frequency that is well beyond the maximum clock rate for AD9106.

     

    Regards,

     

    Marco