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Minimum Frequency offset for Dual tone CW generation in AD9174

Category: Software
Product Number: AD9174
Software Version: Xilinx SDK 2019.1

Hi,

I have a requirement to generate dual tone output from AD9174.For that I am using TPL_DAC_DDS(Internal DDS in Transport layer).

I am able to generate 2 tones with an offset of 1MHz(Ex: 100 MHz & 101 MHz) which can be clearly observed in Spectrum Analyzer, However I am not able to get 2 tones with an offset range between 5 to 20 kHz (Ex: 100 MHz & 100.005/100.020 MHz) which is my requirement. I am trying to program them along with the required offset but unable to distinguish them(as I was able to do for 1M offset) when observed in Spectrum Analyzer. I tried reducing the span but never got 2 peaks.

Is there any such minimum frequency offset that the TPL_DAC_DDS takes to generate 2 tones of different frequencies, or its the chip(AD9174) that has some limitations related to this?

I am using AD HDL for AD9174. Mode 8,Dual Link, Ref_clk = 250 MHz,Interpolation = 12, Fout = 1G.I have attached a snap of the part of the code I am executing to generate dual tone using dds.(This snippet is from axi_dac_core.c)

Regards,

Sourav

Parents
  • Hi Sourav,

    Do you have your resolution BW low enough? With my RBW at 100Hz and span at 45kHz I am able to see a 15MHz offset pair. There shouldn't be a limitation from the 9174-side, so if you have a low enough RBW already and still don't see the tone it you will want to ask on the FPGA forum.

  • My DAC input clock is 3G. I am able to get a 1MHz offset Pair, but not in kHz domain. I will check the RBW value & get back to you soon. I have posted the same in FPGA Forum.

    1.Can I generate dual tone from DAC Internal NCO?

    2.What according to you should be ideal RBW so as to achieve 5~20 kHz offset for a frequency range of 2.5G & above? I will try reducing RBW & Span to a low enough value. By the way we have tried keeping the span in kHz but didn't got 2 tones.

    3. Can this be a limitation of the Internal DDS used in TPL layer(FPGA), any idea?

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  • My DAC input clock is 3G. I am able to get a 1MHz offset Pair, but not in kHz domain. I will check the RBW value & get back to you soon. I have posted the same in FPGA Forum.

    1.Can I generate dual tone from DAC Internal NCO?

    2.What according to you should be ideal RBW so as to achieve 5~20 kHz offset for a frequency range of 2.5G & above? I will try reducing RBW & Span to a low enough value. By the way we have tried keeping the span in kHz but didn't got 2 tones.

    3. Can this be a limitation of the Internal DDS used in TPL layer(FPGA), any idea?

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