AD9154 SYNC lose lock

Hi, All

     I  build a  Wave Generation system by FPGA and AD9154.  FPGA  work as JESD204B  Tx

and AD9154 work as JESD204B Rx.  JESD204B  Lane rate is about 10.64Gbps。 Now  there

is trouble bllock me is that.  AD9154 will assert SYNC low random which means SYNC can not

lock stable.  I  have check JESD204 Link layer parameter setting at FPGA  and find it is the same

as  AD9154  which config by FPGA with SPI.   I  don't know what  many factor lead to the SYNC 

unlock,  what should  I  check . Please give me a guide, Thanks!