We have recently developed a new FPGA board with DAC AD9736. the sampling clock for the DAC is 480 MHZ and we are supposed to generate 70MHZ signal
our settings is as follows
1. input clock 480MHz
2. interpolation - 2X
3. Pin mode
4. output current 20mA
Input sampling clock 480MHz(CLKP,CLKN) we have connected from LTC6951 chip(CML output) - we are generating 480MHz clock from 120MHZ input clock from external and input clock is very clean
the output of AD9736 we are getting a lot of spurious with frequencies such as 10MHz,20Mhz,30Mhz etc... these spurs power levels are only 15 dB down compared to 70MHz which is not desirable. what we can do to eliminate these frequencies and get a Good SFDR?