Hi,
I am using DAC JESD chain(AD RTL) in FPGA to interface with AD9174(DAC) in Vivado Project.
I want to configure the JESD mode(Mode 4 for AD9174) for Dual Link. This mode has L=4,M=4 per DAC cores.
I want to go for dual DAC operation such that (Link0 = DAC0,Link1 = DAC1).
Since dual link would use first 4 lanes(corresponding to DAC0 core) & next 4 lanes(corresponding to DAC1 core) as per its default configurations. When I use the same value to configure JESD_TPL(Transport layer), JESD_LINK(Data link layer), UTIL_XCVR(Physical layer) IPs (AD IPs) in DAC(Tx) JESD chain, then it only gives out 4 lanes as the output of JESD_LINK, and the same for UTIL_XCVR also.
But both JESD_LINK, SERDES(UTIL_XCVR) should give out 8 lanes total since I am using dual link so each links holds 4 lanes each. The data(tx/rx) is also getting halved when I use L=4.(I can't use L=8 with the selected mode 4).
1.So should there be two different JESD Tx Chains in the FPGA for DAC when operating in dual link.(Since the LINK Layer IP, do allow us to select num_of_links, and in the AD9174 chip too there is only 1 JESD chain), so I assumed the same from RTL point of view also.
2.Or Do I need to put L=8,such that in dual link the LINK & UTIL_XCVR IP would understand that the user means L=4(but due to dual link user has mentioned value of L=8),or go with some other approach.
Need some solution/suggestion on the same
Hoping for a quicker response from someone in the community.
I have attached a few screenshots to have some clarity on my doubt.
The yellow mark represents the changes in the number of Tx(GTs) coming out of the JESD_LINK IP after changing to L=4 with number of links = 2.
The XCVR IP (serdes) even gives the same 4 number of lanes even after choosing dual link mode.
Thanks,
Sourav
