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Dual Link JESD setup for independent DAC cores

Category: Datasheet/Specs
Product Number: AD9174

I found this point on Product Highlight section(Page 1) of AD9174 datasheet.

I went through the Start-Up sequence for JESD mode setup and found ways to configure dual link(repeating SPI writes on register 0x300,0x475,0x453 & 0x458) respectively.

I have a doubt. Let's say I want to go for JESD mode 4, having L=4,M=4.Now configuring dual JESD link I would do as asked in the start up sequence section, but how do I know that link 0 corresponds to which DAC core, i.e. DAC0 or DAC1.and similarly for Link1 as well.

I wanted to have M=4 (2x complex(I/Q) channels per DAC core data path), so setting link 0 & link 1 separately don't tell me if M=4 corresponds DAC0 or DAC1 core.

Any suggestions on the same would be of much help.


  • Hi Sourav,

    Single link defaults to DAC0.To change this you need to use the crossbar switch, as I noted in my first response. You can read about that on pg 41 of the datasheet.

    Yes, 0x50FF is fine for a full scale DC tone amplitude. Your configuration sounds fine. To use the main NCO on datapath 0 you need to page channel 0 (W 0x01 to 0x008) before you write your DC amplitude word to 0x148/149. Then page main dac0 (W 0x40 to 0x008) and set bit 1 of 0x1E6 to enable muxing the tone into the main datapath. 0x130 bit 0 is paged by the channel page bits and muxes the DC tone into the channel datapaths, which you do not want since you are muxing in at the main datapath instead using 0x1E6, so you should not set this bit.

  • Okay, I was surrounded with the thought that can we use DAC1 also(separately) with single link, looks like we can using the crossbar settings by writing 0x30A = 0x08 & 0x30B = 0x26.(Please check the values once).

    But I will have only 4 physical lanes coming out of XCVR(from FPGA) for Mode 8 configuration, correct?(It does not matter if we are using Single/Dual link), just writing to the above reg to bring that change for DAC1.

    About NCO configuration, do we need to write 0x01 to 0x008 first, I thought that since we are bypassing channel datapath completely, so writing only 0x40 to 0x008 would do that job for using Main Datapath.(Is it like we have to select the channel which leads to main datapath, even though we are bypassing it, because the flow of data from SERDES to DAC core is anyway passing through both channel & main datapaths).

    Thanks in advance.

  • Hi Sourav, I saw you just posted a related question which I am looking at, but regarding these questions:

    1) If you use single link for mode 8 you will have 4 physical lanes; if you use dual link you will have 8 physical lanes. You can always use the xbar to switch which physical lanes correspond to which logical lanes (and thus to which dac core). So with dual link you basically have two sets of L=4, so 8 total lanes, which by default have phy 0-3 --> logical 0-3 and phy 4-7 --> logical 4-7. You could switch these if you want in the xbar. If you do single link the data will always go out on phy 0-3. By default this maps to logical 0-3 i.e. DAC0 core, but you can mux it to logical 4-7 for DAC1. 

    2) Yes, even with the channels bypassed you have to page channel 0 for main NCO 0 and channel 1 for main NCO 1 when injecting the DC tone. This is because the dc amplitude word is shared between the channel and main datapaths.

  • While operating for NCO only mode, can you tell me if there is any proper calculation for DC word Full scale?

    Because we are getting variations in power level of DAC core output, we wanted to be sure if FPGA is causing something, but we got the same power level(dBm) when tried in NCO only mode.

    I wanted to know if I can try with different values for DC scale, but I am not aware what parameters we need to take care to calculate it and how does it affect if I change it. Currently I am using 50FF(Full scale) which is default.