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Dual Link JESD setup for independent DAC cores

Category: Datasheet/Specs
Product Number: AD9174

I found this point on Product Highlight section(Page 1) of AD9174 datasheet.

I went through the Start-Up sequence for JESD mode setup and found ways to configure dual link(repeating SPI writes on register 0x300,0x475,0x453 & 0x458) respectively.

I have a doubt. Let's say I want to go for JESD mode 4, having L=4,M=4.Now configuring dual JESD link I would do as asked in the start up sequence section, but how do I know that link 0 corresponds to which DAC core, i.e. DAC0 or DAC1.and similarly for Link1 as well.

I wanted to have M=4 (2x complex(I/Q) channels per DAC core data path), so setting link 0 & link 1 separately don't tell me if M=4 corresponds DAC0 or DAC1 core.

Any suggestions on the same would be of much help.


  • Hi Sourav,

    Link 0 corresponds to DAC0 and link1 to DAC1. The physical lanes can be optionally remapped to different logical lanes, of which the first half will correspond to link0 and the second half to link1, as described in the screenshot below. 

    Your JESD mode will be duplicated per link. If you use mode 4 each link uses 4 lanes and 2 complex channels per DAC. You can set the NCOs/gain/etc differently for each link datapath, but the I/Q data is the same for both. Is that what you are asking?

  • Hi KB,

    Ya, I wanted to know the same.

    So if I understood correctly we don't have to manually set lanes to the link they belong to, its just that when we go for Dual link mode, then based on the JESD mode used, it uses that many lanes as x for link0, and increments it (based on L value), & for the second link it starts with x+4(irrespective of the L value) and then increments it the same manner.

    I check the register 0x308 to 0x 30B, I think I should leave it to its default value since as u mentioned that first four corresponds to link0 and the other half to link1.That should be fine correct?

  • Can I work with disabling channel NCO,& just using the channel Interpolation (since the mode I want to go for(mode 4), I have to use both channel & main interpolation to get a desired lane rate that the device can operate with). Actually I wanted to use only main NCO.

    Any suggestions please on the same.

  • 1. Yes you can leave 0x308-30B as is, the default mapping is each physical lane corresponds to the same numbered logical lane.

    2. Yes, you can use both channel and main interpolation and only the main NCO.

  • Yeah, looks proper! Got it.

    I have a one more concern to discuss about.

    Looking at table 13, for the modes 8 & 9, it says to have 2 channels/DAC core, according to which value for M should be 4 per link. But Table 15 claims to have M=2 for mode 8 & 9, which is technically not possible with complex dual channel/DAC. 

    Needed some clarification on the same please.

    Provided that I want to go for Default Modulator switch configuration(real inputs to each DAC core coming from their respective data path), I think that should be possible to achieve with modes 8 & 9.Correct?

  • Yes, modes 8 and 9 used in the default modulator switch configuration have M=2, 1 channel per core. The note in table 13 showing 2 channels per core is only valid in the below modulator switch setup: each main datapath has a single complex channel, but the two are summed after the main NCOs and sent to a single daccore, which is what is meant by 2 channels per core. If you do not use configuration 3 then the single channel-fed main datapaths go straight to each dac, and you have 1 channel per dac.

    Another note is that the 2464 iBW listed for modes 8/9 in your screenshot is also only valid using the modulator switch config below, where two wideband channels are summed into one dac. In the default config you will have 1540*0.8=1232MHz iBW.

  • this was the point I was missing.

    I would go with default configuration for mode switch for mode 8/9.

    Could you please g through this one raised a few days back by me. You can just give some insight to it.  Dual link JESD mode in AD RTL FPGA 


  • Hi KB, 

    just a little clarification needed, if I use single link for mode 8/9 having L=4, then L=4 corresponds to both DAC0 & DAC1, correct? It doesn't gets divided like 2 for each DAC cores as it happens for dual link case u mentioned above?

  • Hi Sourav,

    The modulator switch config shown above is a special setup case. Generally dual link means you duplicate the jesd mode for each dac (i.e. you have 8 total available lanes, so in mode 8 you would give 4 lanes and M=2 (1 channel) to dac0 and 4 lanes M=2 to dac1, so the basically you duplicate mode 8 for each dac. For the case shown above you have a dual link, but the two main datapaths are summed together and sent to one dac core. I wouldn't worry about that setup for now if you don't need it.

    In general, if you have single link you are running dac0 only, regardless of your jesd mode. Any mode that uses L>4 can ONLY be single link, since you only have 8 available serdes lanes (so if you had an L=8 mode, you can only have 1 link). If you use mode 8 in single link then L=4 corresponds to DAC0 (all data on the 4 lanes goes into the dac0 main datapath and there is no data in the dac1 datapath). It is not split between the dacs. If you ran mode 8 dual link, lanes 0-3 go to dac0 and lanes 4-7 go to dac1. Does that make sense?

  • Hi Kberry,

    I understood the points you have mentioned above, its pretty much clear through! So with Single link I can use either DAC0 or DAC1 correct? I mean as you said all the data on the 4 lanes will go into the main datapath on either DAC0 or DAC1 based on the CHANNEL_PAGE reg(0x008) selection.

    One more thing, I wanted to use NCO ONLY mode, for that keeping the DC tone reg(0x148 & 0x149 = 0x50ff which the datasheet suggests) will be fine ?  I want to use(mux) DC input to the final DDS(NCO) & program the NCO for 1GHz (FTW, reg 0x114 - 0x119) & disable NCO calibration.This configuration wise would be fine ,correct?

    Also, the register 0x130Bit[0], is used to enable/disable the DC test tone mode. This is common to both channel & main datapath correct?(Since this configuration is written in DDSC_DATAPATH_CFG section and there is nothing mentioned about it in DDSM_DATAPATH_CFG , so I had a doubt).

    Thanks in advance.