I am using complex dual channel(Dual DAC mode) of AD9174.
I want to operate at >=12GSPS DAC rate. I have input clock of 3G which by using internal DAC PLL ,I'm making it to 12G.
I want to use 1 complex channel per DAC core.(Preferred to bypass channel data path, but due to issue in selecting proper JESD mode, I can go with both channel & main interpolation to get lane rate within the limit).
I wanted to go for single link mode of configuration with M=4(since I am using both complex channels), but with the modes for M=4, except JESD mode 4, I am getting a lane rate which exceeds the limiting boundary of the device , i.e. 15.4 Gbps. Then I found a statement in the feature page of AD9174 datasheet stating, "The AD9174 can be alternatively configured as a dual DAC, with each DAC operating across an independent JESD204B link".
I am confused with that the above statement wants to convey. It raised certain questions to me like:
1. If I use dual link, do I need to have two different JESD chains for DAC in FPGA(meaning every layer(AD IP) would be repeated twice)?
2. If I use dual link with only one JESD chain, how lanes will be divided between the links.
3. With the above statement, what I understood is having one complex (I/Q) channel per DAC core ,i.e. M=2 for each link, correct ? (irrespective of choosing channel/main data path)
4. What is the advantage of having dual link, as per the datasheet we would have the same JESD values for a given mode..so with the above requirements listed, can't I go with single link?
Any suggestions on choosing a proper lane rate with the above required configurations would be of much help.
Can't I use dual DAC operating at single JESD link with M=4?
[edited by: sb0844 at 8:03 AM (GMT -4) on 23 Sep 2022]