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Product Number: AD9780
In our application, we are connecting the AD9780 to a Xilinx Zynq UltraScale+ MPSoC. We are driving the LVDS data lines directly from the MPSoC. One of our developers is noticing that the “LVDS low” and “LVDS high” bits are set in the Seek register (0x06). The datasheet doesn’t give much information on what these bits mean other than the inputs may be above/below link specifications. Do you have any more information on what that means? Are there any known special considerations needed when connecting to these specific Xilinx devices?
This is the output spec from the MPSoC/FPGA for the HP I/O banks:
