I'm using a VCU128 FPGA board to push data to a DAC9172 on the HTG board (part number: HTG-FMC-12ADC-16DAC). On FPGA, I use JESD204 IPs from Analog Devices to communicate with AD9172 through multiple gigabit lanes. The DAC9172 was configured to operate at mode 21 with DAC0 successfully. My questions are:
1. Is it possible to configure the DAC9172 at mode 21 with DAC1? If it was possible, which change do I have to make to achieve that? I tried to change the main data page (reg 0x008) but it didn't work.
2. Does the phase "Link 1" represent the link for DAC1? QBD0 and QBD1 are used for DAC0 and DAC1 respectively, is it right?
3. I saw that in your datasheet the QBD1 is enabled only in dual-mode so I thought DAC9172 can only work in two modes: single link (DAC0 only) and dual links (DAC0 and 1), am I right?
Thanks in advance.