Mode selection for AD9176

Hi Yiqi, thank you for your interest in the AD9176.

The minimum DAC update rate is 2.91 Gsps, so mode 10 with 4x coarse interpolation to 2.4Gsps would not meet this requirement. Assuming you do not need dual channel functionality, you could use mode 3 (max 770 complex msps input datarate) and choose your channel and main datapath interpolation as listed in Table 13 in the datasheet to achieve your desired output frequency for either single or dual links.

The difference between modes 8/9 and 10/11 is the number of lanes. Because 8/9 use half the lanes for the same converter count (M=2) the allowable input datarate is halved compared to the 10/11 modes, and they can be used in dual link modes (whereas 10/11 use all 8 lanes and thus can only be used in a single link). Because the datarate is halved in 8/9 they also require interpolation (due to the minimum DAC update rate), so they cannot be used in real only mode.

Thanks,

KB

Hi KB,

Thanks very much for your reply, 

Thanks, we will consider your suggestion of mode 3. The reason why i didn't choose Mode 3 in the first place is because, according to the lane rate calculation equation, the lane rate of Mode 3 with 770Msps is as high as 15.4Gbps. And our requirement of 600Msps would require 12Gbps. I haven't had any experience with PCB routing of such high data rate and it's EMI concerns ( is my this calculation and assumption correct?).

Just to double confirm, can I also check

If i use 4x interpolation filters for waveform shaping instead, ( with I Q input to DAC at 1200Msps instead of 600M). In mode 10 with 4x =4.8G It can meet the min 2.91Gsps requirement. And I can also use on-chip PLL with a reference clock of 50M (m-=2, n=48) ? 

Thanks and regards,

Yiqi

Hi Yiqi,

You are correct about the high lane rates. Your suggestion for mode 10 setup with a 1200MSPS I/Q input is perfectly feasible. Another option to get the same lanerate would be to use your original 2x interpolated 600MSPS from the FPGA and use mode 8/9 with 6x or higher main datapath interpolation.

Yes, you can use the on-chip PLL as you described for the mode 10 setup, but you will need to set bit 0 in register 0x094 in order to use the VCO divisor of 2 such that: fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1) becomes: (8*48*50MHz)/2/2=4.8GHz. Alternatively you can use M=1 and N=24 with the VCO undivided, or any other combination of these 3 components to get your 4.8GHz output using your 50MHz ref clock (as long as 50MHz < (ref clock / M) < 770MHz to satisfy the phase frequency detector block specs).

Regarding EMI concerns: because the JESD traces are differential pairs they are fairly resilient to coupling with good common mode rejection. If you are worried about environmental factors, a stripline implementation is preferable to surface-level microstrip traces for ground plane protection above and below the traces, but this can overcomplicate the PCB design. If you are interested, you can download the IBIS models under tools & simulations on the 9176 product page. You can then input your own trace model settings to assess any coupling effects.

Thanks very much for your answer and the useful simulation tool, I can continue from here.

Btw 

The internal VCO operates over a frequency range of 8.74 GHz
to 12.4 GHz, with additional divider settings if a lower DACCLK is
required by the application. The DAC clock rate is user
configurable to be the VCO frequency (8.74 GHz to 12.4 GHz),
the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the
VCO frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting
Register 0x094, Bits[1:0]. See the Start-Up Sequence section for
instructions on how to program the PLL.

Doesn't this mean that i have to use VCO divisor of 2?

Regards,

Yiqi

Hi Yiqi,

Yes, so if you set bit 0 to 1 in 0x094 you should be all set.

Best wishes,

KB

Hi Yiqi,

I realize the IBIS models are for lower speeds -- we don't have an AMI model for the 9176, but you can request the 9177 version which should give you the same results for JESD evaluation (9177 AMI request form)

Hi, 

With the agreed Mode 10 of JESD, i have some questions on the reference clock selection

1) I will use only 1 DAC.  Is SYSREF +/- signals necessary, if not, just leave them unconnected is ok?

2) For the DAC eval board, can I use external 50Mhz for testing and bypass the hmc7044?

Hi Yiqi,

1. SYSREF is not required unless you are operating in Subclass 1 mode for deterministic latency. In Subclass 0, an internal processing clock acts as the alignment edge, so you can leave those pins unconnected.
2. Yes, you can bypass the HMC chip. In order to use direct clocking you will need to replace caps C36 and C38 with C34 and C35, input your low noise 50MHz source to J34, and enable the DAC PLL with the settings previously discussed.

Best wishes,

KB

Thanks!