Hello,
we are experiencing a problem similar to the one described in this post:
we have a custom board that uses the AD9144. We were able to set up the JESD link successfully for several configurations, but one of them (that happens to be the one that we want to use) has an unstable behavior. Upon boot, the system starts correctly roughly 1 time out of 3 (randomly). To see if the system is OK, we check the default 40 MHz sine wave from the internal DDS on the oscilloscope. When it starts correclty, the 40 MHz sine wave is visible and it remains OK until the next reboot. When it fails, no output is visible on the oscilloscope and it stays this way until the next reboot.
When it fails, the jesd_status ouptut looks fine (all "green", SYSREF captured, etc), but checking the AD9144 SPI registers reveals that "blanking mode" is activated (see linked post).
The only differences when I compare the SPI registers (the ones listed in the AD9144 datasheet) are:
0x038 SYNC_LASTERR_L (good: 0xF4 bad: 0xEB)
0x147 SOFTBLANKRB (good: 0xC0 bad: 0x00)
0x302 DYN_LINK_LATENCY_0 (good: 0x0 bad: 0xF)
Some details about the configuration:
The configuration of the AD9144 we want is with 128 MHz data input rate, interpolation x2 (done with the AD9144 internal interpolator), this gives a 256 MHz final sample rate.
The relevant portion of our device tree is the following:
&axi_quad_spi_daq {
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9144_spi: ad9144@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "ad9144";
reg = <0x1>;
spi-cpol;
spi-cpha;
spi-max-frequency = <1000000>;
clocks = <&axi_ad9144_jesd>, <&idt8t49n1012 0>, <&idt8t49n1012 1>;
clock-names = "jesd_dac_clk", "dac_clk", "dac_sysref";
txen-gpios = <&axi_gpio_1 41 8>, <&axi_gpio_1 42 8>;
reset-gpios = <&axi_gpio_1 40 8>;
irq-gpios = <&axi_gpio_1 34 8>;
adi,interpolation = <2>;
adi,jesd-xbar-lane0-sel = <0x0>;
adi,jesd-xbar-lane1-sel = <0x1>;
adi,jesd-xbar-lane2-sel = <0x2>;
adi,jesd-xbar-lane3-sel = <0x3>;
adi,jesd-xbar-lane4-sel = <0x4>;
adi,jesd-xbar-lane5-sel = <0x5>;
adi,jesd-xbar-lane6-sel = <0x6>;
adi,jesd-xbar-lane7-sel = <0x7>;
adi,jesd-link-mode = <6>; // 4 is the default
adi,jesd-subclass = <1>;
};
};
&amba_pl {
/delete-node/ ad_ip_jesd204_tpl_dac@44a50000; // this becomes axi-ad9144-hpc@44a04000
/delete-node/ axi_adxcvr@44a30000;
axi_adxcvr_0: axi-ad9144-adxcvr@44a30000 {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x44a30000 0x10000>;
clocks = <&idt8t49n1012 2>;
clock-names = "conv";
adi,sys-clk-select = <XCVR_CPLL>;
adi,out-clk-select = <XCVR_REFCLK_DIV2>;
adi,use-lpm-enable;
#clock-cells = <0x1>;
clock-output-names = "dac_gt_clk", "tx_out_clk";
};
axi_ad9144_jesd: axi-jesd204-tx@44a20000 {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x44a20000 0x4000>;
interrupt-parent = <&axi_intc_0>;
interrupts = <22 2>;
clocks = <&clk_bus_0 &axi_adxcvr_0 1 &axi_adxcvr_0 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
adi,octets-per-frame = <2>;
adi,frames-per-multiframe = <0x20>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <2>;
#clock-cells = <0x0>;
clock-output-names = "jesd_dac_lane_clk";
adi,subclass = <1>;
};
axi-ad9144-hpc@44a50000 {
compatible = "adi,axi-ad9144-1.0";
reg = <0x44a50000 0x10000>;
spibus-connected = <&ad9144_spi>;
adi,axi-pl-fifo-enable;
};
};
The JESD configuration we are trying to use is number "6" that has 2 converters and 2 lanes (M=2, L=2, S=1, F=2, HD=0, N=16, NP=16).
On the FPGA side, we modified the design accordingly and regenerated the transceiver configuration with the Xilinx transceiver wizard for our target configuration. We are using the CPLL, but switching to QPLL seems to give the same behavior.
To feed the input clock we are using an IDT8T49N1012 clock generator. We are sending 256 MHz as JESD refclk for the AD9144 and 128 MHz for the FPGA, SYSREF = 2MHz for both (side note: to make the system work we had to write a kernel module for the IDT8T49N1012 that is able to respond to "clk_set_rate" and "clk_get_rate" API calls required for the JESD kernel drivers).
I'd like to mention that we tested other configurations that didn't have this problem, for example this one worked fine: 2 converters @256 MHz data rate with x2 interpolation (512 MHz final sample rate).
Another point, I noticed that on the datasheet there is no mention of the minimum DAC sampling rate and I'm not sure if ours (256 MHz sample rate after interpolation) is acutally supported.
The questions is: do you have any suggestions to debug this issue?
cleaned up gpios in device tree
[edited by: andrearu at 1:29 PM (GMT -4) on 6 Jul 2022]
