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Low signal level from AD9172-FMC-EBZ

Category: Software
Product Number: AD9172-FMC-EBZ


I'm trying to use AD9172-FMC-EBZ in NCO-only mode. I bring up the JESD link and then configure the data chain to use the main 48-bit NCO only, using the ADI no-OS API. It seems to work, but the DAC output signal level is only about -73 dBm, when the DC amplitude register has value 0x7FFF. Decreasing this register value decreases the output signal level correctly.

I have verified that register 0x1E6 bits 0 and 1 are as expected.

Ramp up/down block is disabled. I also verified that forcing ramp down disabled the output signal.

We also bought AD9176-FMC-EBZ, and it behaves exactly the same way, so it is not a FMC module hardware problem. Seems that I just fail to program the converter correctly.

The datasheet says on page 66 that "Mode 3 and Mode 4 can be used to generate a single-channel or dual channel NCO only mode of operation, respectively." Does this mean that the other JESD modes can't be used in NCO-only mode? I don't see why that would be the case. For example, here Matti uses mode 0:

Synchronizing phases of DAC0 and DAC1 in AD9173 NCO only mode

The carrier is our own and well tested with other FMC modules, so I don't believe it causes any troubles here.

I have tried a couple of modes, but the result is always the same. I'm kind of stuck with this, so any advices are warmly welcomed.

Br, Kari

  • Hi Kari,


    In NCO-only mode the JESD links do not need to be up -- any data on the SERDES interface will not be presented to the DAC while NCO-only mode is enabled. However, the JESD_MODE register does control the clocking to the digital datapaths, so if you were to use channelizers (vs main dc test mode) you would need to set an appropriate JESD mode (mode 3 has M=2, i.e. one complex channel enabled, mode 4 has M=4, 2 complex channels). If you are using the main NCO only the JESD mode shouldn't matter (though it will limit interpolation values). Matti is using the dual link setup with DC Test mode set to "main" so the JESD mode is not relevant.


    Can you check if the DDSM_NCO_EN bit is set in 0x112 and the DAC power down registers in 0x090 are cleared? In main NCO mode with the power down bits set I see an output amplitude of -57 dBm vs -2 dBm with them cleared. If you are using ACE and can print the register values (Exporting Interaction With Hardware [Analog Devices Wiki] ) we can check a little further. Thank you!



  • Hi,

    I use function ad9172_init() to initialize the DAC, so the idle control register gets properly set in function dac_init_sequence(). Register x112 is set to value x7C.

    The DAC is set to use mode 10, input sample rate from JESD 20*122.08 MHz, 4x interpolation by main channel 0.

    I found out that there seems to be a difference between AD9172 and AD9176, what it comes to DAC max current setting. AD9172 seems to have 10-bit setting (registers x59 and x5A), while AD9176 has 8-bit setting (register x5A). However, the formula for the full-scale current is the same. If that is correct, the max current of AD9172 is 4x the max current of AD9176.

    As I wrote my test code originally for AD9172, I also wrote to register x59 of AD9176 to set up the full-scale current. Interestingly, that register exists in the memory space of AD9176, but it is not documented in the datasheet. The value of this register seems to be one reason why I got low signal level. The value seems to control the curve shape of x5A register value vs maximum output power.

    Another reason for low signal level was low signal frequency in my original test code (110 MHz).

    I see that the DAC is in IDLE mode occasionally after initialization. Output power is about -57 dBm in that case, as Kate wrote above. Is there some built-in mechanism in the DAC which could cause it to go in IDLE mode? Too high temperature, too low voltage or something like that? Or maybe I have a SPI problem?

    Below are output power curves with two settings of register x59. The signal frequency is 3 GHz.

    Br, Kari

  • Hi Kari,


    Register 0x59[7:4] controls the minimum output current of 15.625mA with a value of 0xA0 (10/(2^4)*25). Writing 0x03 to this register drops your starting output current, which is why your first curve in the image below has such low value. Using r0x59[1:0] combined with r0x5A[7:0] as part of your output current calculation doesn't increase the available output current, but rather increases the resolution by 2 bits. Because there is a default setting of 0xA0 for r0x59 the equation in the datasheet shows a division factor of 256; updating to 10 bits by writing to 0x59[1:0] increases that resolution factor to 1024. I would advise leaving r0x59 at the default value.

    Regarding the occasional idle state: you mean after you run the initialization sequence with the powerdown bits cleared they become set at some point later on and drop your output? Can you give your full initialization sequence in that case? I am not sure when those bits would get set. 

    Best wishes,


  • Assumed answered. Pleawe let us know if there are further questions.