Category: Hardware
Product Number: AD9161
Hi, I’ve faced with issue with JESD204B mapping for DAC AD9161.
DAC works with following parameters: L = 8; M = 2; N = 16; S = 2; F = 1.
For data forming, I use INTEL Arria 10GX EVB with JESD204b Intel IP core. IP core was configured with same parameters. I form vector [255:0] with next data order:
I used DPG downloader to generate single tone pattern with next parameters:
Relied upon DS for DAC and IP core, I’ve managed octet’s order for both converters:
Octets was forming with using this order (this example for I samples, Q samples are the same):
With this configuration, I can’t achieve normal single tone:
Did I make some mistakes or misunderstandings?
Is it correct that with M=2 I need to send complex IQ input data?
