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AD9172 channel datapaths

Category: Datasheet/Specs
Product Number: AD9172

Hi,

I am testing AD9172 JESD with FPGA .In DAC ,I am using JMode=8 dual link.as per datasheet , main interpolation is 8 ,channel interpolation is x1 (which means channel datapaths are bypassed).

how jesd data will come through that channel data paths? and am using main nco s!

Thanks

Venkatesh k