We plan to use AD9172 to drive HMC8193 I/Q mixer. The final signal frequency is in range of 4 to 8 GHz. The BW needed is 1.5 GHz. The data rate we planned to use was 2.5 Gsps. No interpolation was planned. So, simply I samples on DAC0 and Q samples on DAC1.
However, we found out that the minimum DAC update rate is 2.91 Gsps. Because of our FPGA, and its JESD core in particular, we are not able to reach such high sample rate, at least not in 16-bit mode. Therefore, we'd like to use 2x interpolation to get 5 Gsps final sample rate. As the interpolation filters require complex data, I'm not sure if there is a digital data path to do what we want.
I guess it would go somehow like this:
- send I samples on JESD lanes 0 to 3
- send Q samples on JESD lanes 4 to 7
- switch the I/Q samples to DAC0 only, DAC1 would not be used
- Interpolate by 2 using the digital chain of DAC0
- Use the modulator switch Configuration 2 to forward DAC0 I samples to DAC0 core, and DAC0 Q samples to DAC1 core.
Is this possible? Or is there some other way to reach what we want?