Post Go back to editing

AD9707 output extremely noisy

Hello, I received a board with an AD9707 on it.

It seems they are trying to turn the differential signal to a single ended one.

I was told to first measure across R199, but my output looks terrible.

Clock is differential input to the AD9707, 100 MHz

I am sending a sine wave from the FPGA at 17 MHz.

I tried changing the clock polarity in the AD9707 to latch on the negative edge but that makes no difference. So I don't think this is a problem with the digital inputs to the AD9707.

Are the outputs for IOUTA and IOUTB in a valid configuration? 

Top Replies

    •  Analog Employees 
    Mar 30, 2022 in reply to JailBoss +1 suggested

    Hello  ,

    Glad to hear that you were able to generate a less noisy output.

    From the schematic you shared, It looks like there is possible impedance matching issue.

    First thing is to confirm the input…