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Jesd204b link synchronization of ad9172

I use Xilinx's FPGA to connect to ad9172.

The input data of my DAC is DDS, jesd can be synchronized, and DA can work normally.

However, the data after DDR cache collected and processed by ad can not be synchronized with the jesd of DA.

This part of the data is correct after being processed by ILA and MATLAB,

Only by changing the input data, the synchronization of jesd link is pulled down

  • Hi,  if my understanding correct,  with the sinewave generated by DDS to DAC,  the serdes link correctly, DAC output correctly.   Changed to the  normal working data,  the  jesd link crashed        So, first  pls check the power supply for the  AD9172 on the AD9172 pins,  specially for the DVDD and serdes related p.s.   By different toggle  rate of the digital circuits implied by  DDS or normal day feed in, may cause high  IR drop on the PCB trace.  

  • I use the power supply scheme recommended in the official manual. Adp1763acpz-1.0-r7 is used to supply power to dvdd, SVDD and davdd, another adp1763acpz-1.0-r7 is used to supply power to avdd, adm7154acpz-1.8-r7 is used to supply power to dvdd1p8 and avdd1p8, and each power supply is treated with copper coating, which may not be the problem of power supply. I suspect it is caused by unstable program,