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AD9172 programming

Hello everyone,
I am working with the HTG-FMC-14ADC-16DAC mezzanine board and now I am trying to configure the ad9172 DAC.
Faced with the problem that I am not getting a sine wave output, maybe you can tell me where I am making a mistake.
I want to use NCO only mode. Without using JESD, no modulation, i.e. the simplest option.


The DAC input frequency is 122.88 MHz. At the output I want to get about 600 MHz.
When setting the registers I use PLL and DLL locked (bit 1=1). But when reading DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0) after an update request, DDSM_FTW_LOAD_ACK (Register 0x113) Bit 1 must be high. But when reading it, I get ACK bit=0.
Which leads me to several questions.
1. Is it possible to bypass/not use/disable channel NCO and use only the main channel DAC0/DAC1.
2. Do I need to use full start up sequence if I don't use JESD. Can I leave these registers untouched at all like I do?
Also I have some assumptions about my possible errors and so I will ask a couple more questions. (maybe you will find an error in my settings).
1. How to program the FTW registers correctly if integer NCO 48 bit is used.
2. How to correctly program the DDSC amplitude if we only use main nco? Is it required to query channel NCOs and set register 0x130 to 1 (channel mux ddsc_en_dc_input) when accessing ddsc.
Here is my setting of the registers:

assign AD9172 [N] = {register, value}       //16bitADRESS+8bitVALUE //hexadecimal
//---------------PowerUp(49)----------------
assign AD9172 [0] = {16'h000, 8'h81};       //pulse reset
assign AD9172 [1] = {16'h000, 8'h3c};       //adress increment & SDO active
assign AD9172 [2] = {16'h085, 8'h12};
assign AD9172 [3] = {16'h091, 8'h00};       //Analog clock receiver power-down. 0x1 def
assign AD9172 [4] = {16'h206, 8'h01};       //PHY reset control bit. Set this bit to 1 to take the PHYs out of reset during deviceoperation.
assign AD9172 [5] = {16'h705, 8'h01};       //Enable bootloader. This bit self clears when the boot loader completes or fails.
assign AD9172 [6] = {16'h090, 8'h00};       //Power UP DAC0 & Power UP DAC1

//----------------DAC_PLL(50)----------------
assign AD9172 [7] = {16'h095, 8'h00};       //Enable the DAC PLL synthesizer by setting Register 0x095, Bit 0 to 0
assign AD9172 [8] = {16'h790, 8'h00};
assign AD9172 [9] = {16'h791, 8'h00};

assign AD9172 [10] = {16'h796, 8'hE5};
assign AD9172 [11] = {16'h7A0, 8'hBC};
assign AD9172 [12] = {16'h794, 8'h08};
assign AD9172 [13] = {16'h797, 8'h10};
assign AD9172 [14] = {16'h797, 8'h20};
assign AD9172 [15] = {16'h798, 8'h10};
assign AD9172 [16] = {16'h7A2, 8'h7F};

//wait100ms


assign AD9172 [17] = {16'h799, 8'hA};		//~~N divider N=10  
assign AD9172 [18] = {16'h793, 8'h18};		//M divider M=1
assign AD9172 [19] = {16'h094, 8'h00};		//The DAC clock rate is userconfigurable to be the VCO frequency (8.74 GHz to 12.4 GHz),the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or theVCO frequency divided by 3 (2.92 GHz to 4.1 GHz)by setting Register 0x094, Bits[1:0]
assign AD9172 [20] = {16'h792, 8'h02};		
assign AD9172 [21] = {16'h792, 8'h00};		

//wait100ms

//----------------DLL_CONFIGURATION(51)------
assign AD9172 [22] = {16'h0C0, 8'h00};
assign AD9172 [23] = {16'h0DB, 8'h00};
assign AD9172 [24] = {16'h0DB, 8'h01};
assign AD9172 [25] = {16'h0DB, 8'h00};
assign AD9172 [26] = {16'h0C1, 8'h68};		//fDAC 9800 (f>4500 => 68, else 48)
assign AD9172 [27] = {16'h0C1, 8'h69};		//fDAC 9800 (f>4500 => 69, else 49)
assign AD9172 [28] = {16'h0C7, 8'h01};



//----------------CALIBRATION(52)------------
assign AD9172 [29] = {16'h050, 8'h2A};
assign AD9172 [30] = {16'h061, 8'h68};
assign AD9172 [31] = {16'h051, 8'h82};
assign AD9172 [32] = {16'h051, 8'h83};
assign AD9172 [33] = {16'h081, 8'h03}; 

//----------------CHANNEL NCO's------------
assign AD9172 [34] = {16'h008, 8'h3F};          //CH 0-5
assign AD9172 [35] = {16'h146, 8'h00};	        // Gain LSB.  Gain = 0, gain code = 0.
assign AD9172 [36] = {16'h147, 8'h00};	        // Gain MSB.
assign AD9172 [37] = {16'h130, 8'h1}; 	        // enable channel NCO

assign AD9172 [38] = {16'h148, 8'h7F};          //DDSC AMPL LVL
assign AD9172 [39] = {16'h149, 8'h7F};

//----------------MAIN NCO's------------
assign AD9172 [40] = {16'h008, 8'h40}; 
assign AD9172 [41] = {16'h1E6, 8'h2};      //MUX DDSM
assign AD9172 [42] = {16'h112, 8'h8};	// enable NCO and NCO modulus ddsm_mode 00; nco_en 1; modulus 0;ddsm sideband 0;..0;

assign AD9172 [43] = {16'h114, 8'h0};       //DDSM_FTW [7:0]
assign AD9172 [44] = {16'h115, 8'h0};
assign AD9172 [45] = {16'h116, 8'h0};
assign AD9172 [46] = {16'h117, 8'h0};
assign AD9172 [47] = {16'h118, 8'h0};
assign AD9172 [48] = {16'h119, 8'h10};      //DDSM_FTW [47:40]
assign AD9172 [49] = {16'h113, 8'h1}; //113 W bit 0=1 FTW upd request

//----------------cleanup------------
assign AD9172 [50] = {16'h085, 8'h01};
assign AD9172 [51] = {16'h008, 8'h40};
assign AD9172 [52] = {16'h596, 8'h0C};

//------READ-----------------------------------------------------
assign AD9172 [53] = {16'h87B5, 8'h01};		//PLL locked
assign AD9172 [54] = {16'h80C3, 8'h01};		//READ DLL
assign AD9172 [55] = {16'h8113, 8'h00};     //read bit 1 ACK bit FTW
assign AD9172 [56] = {16'h8119, 8'h10};      //DDSM_FTW [47:40] R

If it is possible, please share who can with working register programming options please.

Regards, 



Code edit
[edited by: AlexanderBary at 6:10 PM (GMT -5) on 31 Jan 2022]