Post Go back to editing

AD9707 do I need to separate DVDD AVDD CVDD ?

I am designing a board with 2 AD9707 chips. I do have switched power supply generating 1.8V_digital. It is then filtered (L and many C) and used to supply CVDD and AVDD,

I am afraid to allow 1.8V_digital anywhere near my analog area of my board. Therefore I would like to connect DVDD simply together to my filtered (analog) 1.8V together with CVDD and AVDD.

Are there strong practical arguments to keep these VDD separated as in the evaluation board ?

Should power supplies be kept separate between both AD9707 chips (there are using synchronous clock) ?

  • Currently I have 1.8V_digital supplying directly DVDD. Bad idea?

  • Hi Motyl, 

    The supporting team for AD9707 will respond shortly, but meanwhile I have a few comments. Generally, in any mixed signal design it is a good idea to isolate supply domains from one another. Sometimes filtering is good enough (or even a ferrite bead with good PCB layout), but otherwise we use an LDO to boost the supply rejection; AVDD and CVDD connect directly to bias nodes, and the on-chip rejection isn't great, possibly 10-20dB. If your 1.8V switcher generates an Fsw spur that's sufficiently high, on either AVDD or CVDD, it will modulate onto the output. In addition, if CVDD carries sufficient clock energy, maybe 4dBm, it will couple into AVDD and impact your clock spur - could be constructive or destructive, and the spur will likely change in amplitude on every power cycle (sometimes this matters, other times it does not).    

    LT3045 is a go-to part, has excellent rejection, albeit at 500mA max.  

    Some switchers have "spread spectrum" like modes, e.g. ADP5056, where Fsw is adjusted according to loading - this can cause issues to phase noise performance, more so than a stationary spur at a fixed frequency. 

    in short, isolating supply domains is generally needed, along with proper bypassing of all the domains. proper PCB design and layout are also a must, especially in chips that allow interpolating the data (which have multiple clock domains and the resulting Fs/N spurs). I would suggest to use the EVB as a reference, and make reductions only when a design dictates it, based on empirical data - wiring the supplies together on an ad9707 EVB from a switcher eval board, or even measuring PSMR, can be done.  


  • Hi:

    As the designer of the AD9707 I agree 100% with everything  said in the above response. If you expect to get full datasheet performance then you need to follow the recommendations in the datasheet and as embodied in the EVAL board PCB layout.