Post Go back to editing

AD9163 Sync sygnal low

Hi!

I have ADF4355+HMC362+AD9163+Artix7.

  • DAC sampling frequency: 4.8 GHz
  • 4  lanes, 24x interpolation, M=2, another settings are default

Line rate=2G.

All outgoing frequences are correct. RefClk=100 MHz, global(core) CLK=50 MHz. (2000/40=50). 

First of all I setup ADF4355, then AD9508, then AD9163.

I can see some (50-70) Sync High signals. After this I can see continouis LOW (0).

Can you help explain why? Where is my mistake? All spi commands:

ADF4355:
12,0x1041C
11,0x61300B
10,0xC03EBA
9,0x2A29FCC9
8,0x102D0428
7,0x120000E7
6,0x350283F6
5,0x800025
4,0x30008B84
3,0x3
2,0x12
1,0x1
0,0x200300

AD9508:
0x15,0x0b,OUT0_Divide_Ratio[7:0] --100 MHz
0x1B,0x17,OUT1_Divide_Ratio[7:0] -50 --core
0x21,0x0b,OUT2_Divide_Ratio[7:0] --100
0x27,0x0b,OUT3_Divide_Ratio[7:0] --100
AD9163:

0x0000,0x18,SYNC_LMFC_STAT0
0x00D2,0x52,SYNC_LMFC_STAT0
0x00D2,0xD2,SYNC_LMFC_STAT0
0x0606,0x02,SYNC_LMFC_STAT0
0x0607,0x00,SYNC_LMFC_STAT0
0x0604,0x01,SYNC_LMFC_STAT0
0x0058,0x03,SYNC_LMFC_STAT0
0x0090,0x1E,SYNC_LMFC_STAT0
0x0080,0x00,SYNC_LMFC_STAT0
0x0040,0x00,SYNC_LMFC_STAT0
0x0020,0x0F,SYNC_LMFC_STAT0
0x009E,0x85,SYNC_LMFC_STAT0
0x0091,0xE9,SYNC_LMFC_STAT0
0x00E8,0x20,SYNC_LMFC_STAT0
0x0152,0x00,SYNC_LMFC_STAT0
0x0300,0x00, Ensure the SERDES links are disabled before configuring them.
0x04B8,0xFF, Enable JESD204B interrupts.
0x04B9,0x01, Enable JESD204B interrupts.
0x0480,0x38, Enable SERDES error counters.
0x0481,0x38, Enable SERDES error counters.
0x0482,0x38, Enable SERDES error counters.
0x0483,0x38, Enable SERDES error counters.
0x0484,0x38, Enable SERDES error counters.
0x0485,0x38, Enable SERDES error counters.
0x0486,0x38, Enable SERDES error counters.
0x0487,0x38, Enable SERDES error counters.
0x0110,0x48, 4 lanes, 24x interpolation
0x0111,0x00, Configure the datapath options for Bit 7 (INVSINC_EN), Bit 6 (NCO_EN), Bit 4 (FILT_BW), Bit 2
0x0230,0x02, Lane Rate 1.5 to 3.125, Bit5=0(full rate), Bits[2:1]=01b(divide by 2)
0x0289,0x02, SERDES_PLL_DIV_FACTOR=1
0x0084,0x00, PLL_REF_CLK_RATE b[45]=00, PLL_REF_CLK_PD b0=0
0x0200,0x00, Enable JESD204B block (disable master SERDES power-down).
0x0475,0x09, Soft reset of the JESD204B quad-byte deframer.
0x0453,0x03, SCR b7=0, and L-1 b[0:4]=3
0x0454,0x00, F-1 b[0:7]=0
0x0455,0x1f, K-1 b[0:4]=11111b
0x0458,0x0F, SUBCLASSV NP-------------------0F
0x0459,0x00, JESDV=A b[7:5]=000, S-1 b[4:0]=0
0x0475,0x01, Bring the JESD204B quad-byte deframer out of reset.
0x0201,0x0F, говорим, какой лэйн не используется.
0x0039,0x00, +-24 SYSREF.
0x02A7,01,----
0x02AE,01,----
0x029E,0x1f, Override defaults in the SERDES PLL settings (private).
0x0206,0x00, Reset the CDR.
0x0206,0x01, Enable the CDR. !!!01
0x0280,0x01, Enable the SERDES PLL.!!!01
0x0300,0x01, Enable SERDES links (begin bringing up the link).
0x024,0x1F,Clear the interrupts.
0x4BA,0xFF,Clear the SERDES interrupts.
0x4BB,0x01,Clear the SERDES interrupt.

Thank you!


Parents
  • Hi,

    If I understand correct, you are using 100 MHz reference to ADF4355 and your VCO frequency is 4800 MHz. If your PFD frequency is 100 MHz you should follow a special programming sequence as given in Page 29. Not sure if the root cause of your problem is related with this but it should be corrected. 

    Kudrt

Reply
  • Hi,

    If I understand correct, you are using 100 MHz reference to ADF4355 and your VCO frequency is 4800 MHz. If your PFD frequency is 100 MHz you should follow a special programming sequence as given in Page 29. Not sure if the root cause of your problem is related with this but it should be corrected. 

    Kudrt

Children
No Data