as per title, AD9164 stuck at CGS(0x470 = 0x00). I am suffering this issue which is very similar with this guy: ad9164 sync never goes high , but unfortunately, no answer for this post...
design parameter as: 2.5Gsps with 8 lanes,so the LaneRate is 20*2.5G/8=6.25G. our HW guys probed the clock frequency for both AD9164(2.5GHz) and FPGA(GTH ref clk = 156.25MHz) . it's correct frequency with good SI quality, also probed serdes lane, the FPGA is transmitting K28.5 on all 8 lanes, and lane rate is correct(6.25G).
the AD9164 can output correct sine tone when i set NCO only mode.
JESD related bring up follows start-up in datasheet, register setting 0x110 = 0x80, 0x289 = 0, 0x84=0, 0x230=0x20; status bit: 0x604=1'b1;0x92 =1(DLL lock), 0x281=1(PLL lock). all NIT/UEK/BD error counter is 0.
FPGA QPLL never loss lock.
but the SYNCOUT always stuck at 0, never toggling. I checked many post, seems the clock/frequency usually cause this problem, besides the above information i listed, could you give me more clue to find out the root cause?