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AD9164 stuck at CGS

Hi

as per title, AD9164 stuck at CGS(0x470 = 0x00). I am suffering this issue which is very similar with this guy:  ad9164 sync never goes high , but unfortunately, no answer for this post...

design parameter as:  2.5Gsps with 8 lanes,so the LaneRate is 20*2.5G/8=6.25G. our HW guys probed the clock frequency for both AD9164(2.5GHz) and FPGA(GTH ref clk = 156.25MHz) . it's correct frequency with good SI quality, also probed serdes lane, the FPGA is transmitting K28.5 on all 8 lanes, and lane rate is correct(6.25G).

the AD9164 can output correct sine tone when i set NCO only mode.

JESD related bring up follows start-up in datasheet, register setting 0x110 = 0x80, 0x289 = 0, 0x84=0, 0x230=0x20; status bit: 0x604[1]=1'b1;0x92[0] =1(DLL lock), 0x281[0]=1(PLL lock). all NIT/UEK/BD error counter is 0.

FPGA QPLL never loss lock.

but the SYNCOUT always stuck at 0, never toggling. I checked many post, seems the clock/frequency usually cause this problem, besides the above information i listed, could you give me more clue to find out the root cause?

  • hi

    i would like to append more information here, on my board, the clock tree use HMC7044+HMC7043, FPGA got 1 clk/sysref pair from 7044, and another pair of clock/sysref delivered to HMC7043, then buffer out to several ADs/DAs. now the 7044 PLL2 got locked and others ADC works well. but all on board AD9164 are not working.

    i tried more test as below:

    1, change the clock frequency to 1.6GSPS for AD9164 and change FPGA ref clk accordingly, 8 lane data path bypass mode. i can get continuous K28.5 code on serdes lane at 4Gbps lane rate. but AD9164 still stuck at CGS, 0x470 is always 0x0. moreover, reg 0x30C has random value such as 0x7f or something else, reg 0x30d is always 0xff, all PHY layer error counter are 0s.

    2, use an external clock source to supply 2 sync clock for both AD9164(1.6G) and FPGA(100M), the issue still be there..

    i fully got trouble now, could ADI expert kindly give me some clue? thanks a million!

  • AD9164 ACEPlugin can record the startup sequence and generate the sequence. below is from ACEPlugin. it seems like you programmed 0x230 with the wrong value. it should be 0x28. 

    W 0 18
    W 200 1
    R 6
    W D2 52
    W D2 D2
    W 606 2
    W 607 0
    W 604 1
    W 58 3
    W 90 1E
    W 80 0
    W 40 0
    W 20 F
    W 9E 85
    W 91 E9
    W E8 20
    W 152 0
    W 300 0
    W 4B8 FF
    W 4B9 1
    W 480 38
    W 481 38
    W 482 38
    W 483 38
    W 484 38
    W 485 38
    W 486 38
    W 487 38
    W 110 80
    W 111 0
    W 230 28
    W 289 0
    W 84 0
    W 200 0
    W 475 9
    W 458 F
    W 459 2F

  • Hi Biao,

    first of all, thank you so much, after update reg 0x230, now it works!

    and may i know how to collect the start up sequence file as you list here? i tried in ACE startup wizard, whatever summary or apply button clicked, the ACE only complain no HW/controller acquired blabla.. since i don't have a EVAL board in hand.

  • Hi Leon, 

        refer to https://wiki.analog.com/resources/tools-software/ace/exporting to record macro when click the APPLY button. 

       then save the file. after that, use macro to hex tool(under ACE) to convert it to hex file.

        Yes. you can do above without hardware board.