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AD9707 IOUT_update Timing

Let me ask you about the timing of data update for AD9707.

In FIG2, IOUT changes at the rising edge of the clock.
However, in my measurement result, IOUT has changed after the second CLK rising edge after changing the data.

Therefore, I think that it works as follows, is it correct?
"Trigger DATA at the rising edge of CLK and update Iout at the rising edge of CLK after 1 cycle (after 1CLK)"

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  • Hello  , 

    Happy new year!

    Would you be able to share your schematic or are you using the AD9707 Evaluation Board?

    Also, would you mind sharing your setup and the data for your measurement? 

    Thanks, 

    Lorenz

  • Happy new year!

    Thank you for your support.

    My usage environment is as follows
    ・ Used in PIN mode
    ・ Power supply is 1.8V
    ・ The MSB data was changed from 0 to 1 when the CLK was lowered.

    The IOUT data rises about 24 nS after the next rising edge. (Approximately 4 nS after the second CLK rising edge (CLK = 50MHz))

    It is possible to provide a circuit diagram, but not on the web, but by e-mail etc.
    Please (in that case, please give me the contact information)

  • Thanks for being sharing all the helpful details.

    Unfortunately, this is an old part so there is limited documents available regarding the timing characterization and the current board does not have provision for us to confirm. I just wanted to mention that AD9707 does not have a maximum tpd. Well take a closer look at the timing diagram and update if needed. Thanks!

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  • Thanks for being sharing all the helpful details.

    Unfortunately, this is an old part so there is limited documents available regarding the timing characterization and the current board does not have provision for us to confirm. I just wanted to mention that AD9707 does not have a maximum tpd. Well take a closer look at the timing diagram and update if needed. Thanks!

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