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Questions about AD9128 setting related corrupted data at power on/off test


My customer use AD9129 and they have  some isue on the power on/off test .

They made data source in Xilinx FPGA and generally operation is ok.

But when  they do the power on/off test, they got some issues.

Sometimes, data corruptions are occurred if they do DAC setting thru FPGA.

Sometimes get nomal data and sometimes get corrupted data.

And when they get corrupted data, if they do DAC setting again, they get normal data.

Q) Wolud you let me know your opinions about above issues?

Please advise me.


Below is their DAC setting values and capture files of AD9129 output, for your refierence.

register_buf(0)      <=  X"0000";

register_buf(1)      <=  X"305C";

register_buf(2)      <=  X"0C64";

register_buf(3)      <=  X"0B39";

register_buf(4)      <=  X"0168";

register_buf(5)      <=  X"346D";

register_buf(6)      <=  X"0148";

register_buf(7)      <=  X"3313";

register_buf(8)      <=  X"33D8";

register_buf(9)      <=  X"33D0";

register_buf(10)     <=  X"0D06";

register_buf(11)     <=  X"0AC0";

register_buf(12)     <=  X"1800";

register_buf(13)     <=  X"20C6";

register_buf(14)     <=  X"2103";

register_buf(15)     <=  X"3046";

register_buf(16)     <=  X"1220";

register_buf(17)     <=  X"1181";

register_buf(18)     <=  X"1101";

register_buf(19)     <=  X"0108";


register_buf(20)     <=  X"0081";

register_buf(21)     <=  X"0108";

register_buf(22)     <=  X"0300";

register_buf(23)     <=  X"0400";

register_buf(24)     <=  X"0600";

register_buf(25)     <=  X"0700";       --  Configure FRM to Not used 

register_buf(26)     <=  X"0A00";       -- Data Phase Shift

register_buf(27)     <=  X"0B39";

register_buf(28)     <=  X"0C64";

register_buf(29)     <=  X"0D06";

register_buf(30)     <=  X"1101";

register_buf(31)     <=  X"1220";

register_buf(32)     <=  X"18A0";

register_buf(33)     <=  X"1900";       -- MIX mode disable : For 915MHz frequency 

register_buf(34)     <=  X"1A00";

register_buf(35)     <=  X"20C6";

register_buf(36)     <=  X"2103";       -- Configure Max. Output Power to 3

register_buf(37)     <=  X"2200";

register_buf(38)     <=  X"230C";

register_buf(39)     <=  X"3046";

register_buf(40)     <=  X"33D0";

register_buf(41)     <=  X"345D";

register_buf(42)     <=  X"5000";

register_buf(43)     <=  X"5100";

register_buf(44)     <=  X"5200";

register_buf(45)     <=  X"5300";

register_buf(46)     <=  X"5400";

register_buf(47)     <=  X"5500";

register_buf(48)     <=  X"5600";

register_buf(49)     <=  X"5700";

register_buf(50)     <=  X"5800";

register_buf(51)     <=  X"5C00";

register_buf(52)     <=  X"70FF";

register_buf(53)     <=  X"7167";

register_buf(54)     <=  X"7C40";

Normal output 

Abnormal output

  • Hi , please see the " power-up time " on page 46, how are you doing the power on/off test ? ,  do you disable Iref, i.e The recommended way to power up the AD9119/AD9129 is to power up all parts of the circuit with IREF disabled (by setting Register 0x01, Bit 6 = 1b), and then enable IREF by programming Register 0x01, Bit 6 = 0b.

    regards Brigid