AD9781 dual-port and interleaved LVDS inputs

Hello Markze,

The AD9783/81/80 DAC family only has a single LVDS port which receives multiplexed/interleaved I and Q data words. This family is based off of the AD9747/46/45/43 DAC family which has the dual-port and interleaved single-port options. The wording of the particular feature might have been overlooked on the AD9783/81/80 datasheet which is now lined up for revision. Thank you for pointing this out.

Regards,
Shine

Hi Shine,

Thank for your feedback and confirmation.

It mean that AD9783/81/80 do not have the dual-port feature. Only have interleaved single-port.

The following is the only option for data input:

By the way, if I require only single channel DAC output, shall we just hold DCIP/DCIN input?

Will the sampling in DSS either rising or falling edge? or Only single edge.

Thank for your help in advance.

Thank you.

Mark

Hi Shine,

Thank for your feedback and confirmation.

It mean that AD9783/81/80 do not have the dual-port feature. Only have interleaved single-port.

The following is the only option for data input:

By the way, if I require only single channel DAC output, shall we just hold DCIP/DCIN input?

Will the sampling in DSS either rising or falling edge? or Only single edge.

Thank for your help in advance.

Thank you.

Mark

Hi Mark,

No need to change DCIP/DCIN. If you won't use one of the channels, you can set the applicable power down bit.



Then, keep the data inputs LVDS low for the unused channel.

Regards,
Shine

Hi Shine,

Thank for your feedback.

Understand that we can power down 1 channel.

Might I know how DSS sampling behavior after single channel?

For example, if power down DAC2 and I would like to sample for Q1, Q2, Q3.......

Will data signals are sampled on the edges of DSS by rising (Q1), falling (Q2) , rising (Q3) ........? 

Appreciate your help.

Thank you.

Mark

Hi Mark,

If one of the channels, for example the Q DAC, is disabled, there will be no output at OUT2P and OUT2N but DSS and DATA timing will remain the same. The digital block will still be deinterleaving. But since you won't need the data for the disabled DAC, you don't need an LVDS lane rate that's 2 x DSS frequency. See illustration below:


Regards,
Shine