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I'm studying how to use the AD9172.

Please tell me some questions. (sorry for the rudimentary question.)

1. I don't understand what M(JESD204B param,the converter count (M) ) means? What is the relationship with DAC.

2. I want use JESD mode 8, main x4 interpolation Dual-link. After configuration according to the startup sequence, the DAC has no output.

   PLL locked,  JESD linkup.  


  • Hi,

    1- M is the number of virtual converters. These converters are tied to channelizes which can be summed at the summing node into a main DAC. 

    2- Are you using ADI evaluation board? are you sending data over the JESD link?



  • 1. That is, in mode 18, M0 and M1 of link0  indicate that the I data and Q data input to the main link after conversion?

    2. Not using it.  I'm sending data continuously  after the link is up. My data format is operated according to mode 8 in Table 17 of the ad9172's datasheet. And in this table mode 8's M=4?? 

    thanks agian.

  • 1- correct. 

    2- M = 2 for mode 8 hence why upi see M0Sx and M1Sx. 

    are the links up with no errors?



  • ok, I got it!

    what do you mean about errors?

    I follow the start-up sequence, read 0x7B5 PLL Locked, read 0x0C3 DLL locked, read 0x281 SERDSES PLL locked.

    Do you means JESD errors?  I'm reading this chapter JESD204B serial data interface. It's hard to understand.


  • hi,

    yes, I meant JESD errors. The errors I am referring to are on page 50 under the title "CGS, Frame Sync, Checksum, and ILAS IRQs" are you getting any of those errors. 

    also, another thing to confirm is that the FPGA JESD settings are the same.

    1- One way to confirm that is to use the "Configuration Mismatch Flags". We have a section in the datasheet on page 50 called "Configuration Mismatch IRQ" that checks if the FPGA and the AD9172 are setup with the same parameters when it comes to the JESD link. I would follow that section to ensure proper FPGA settings. 

    2- you can use PHY PRBS testing where you send a PRBS pattern from the FPGA to the AD9172 and see if the AD9172 receive the pattern. this ensures that the lanes have no errors are connected correctly. There is a section in the datasheet about that. it is on page 47 under "PHY PRBS Testing" title. 


  • hi,

    1- This board has no IRQ pin can use. this pin not connect to the fpga.

    2- I use PHY PRBS test. FPGA IBERT send PBRS to the AD9172, test passed.

    3- I see the title "CGS, Frame Sync, Checksum, and ILAS Monitoring", read these register(0x470~0x473) value is "0x0F". maybe this is why my DA1 no output.

    4- can u help me check my setting sequence? my DA0 output is not my desire. I send data (XILINX DDS IP genertate) to the AD9172 using XILIXN JESD204B  IP(2 channel(x4) data is same) . HMC7044 provides system clock.  AD9172's PLL refclk is 300MHz, Fdac=9600M, total interpolation is x8, JESD mode 9. GT LaneRate is 12Gbps.

    this is my setting sequence.

    	// Enbale PLL
        // DAC PLL VCO(8.74~12.4)=(Fref/M)*8*N, DACCLK(2.91~12.4) =VCO/2 ??閳ユ彜CO/3 ??閳ユ彜CO
        // Data Rate = DAC Rate/Total Interpolation = 
        // Lane Rate =  (M/L) * NP * (10/8) * Data Rate
        // PLL Refclk 300M
        // Fvco  9600M
        // Fdac  9600M
        // Fdata 1200M
        // Power-Up and Required Register Writes
        0x00000081,   //81:set soft reset
    	0x00000000,   //00:disable soft reset [4:3]:11, spix4,00,spix3(default),
        0x00009100,   //Power up clock receiver.
        0x00020601,   //Take PHYs out of reset.
        0x00070501,   //Enable boot loader
        0x00009000,   //Power on DACs and bias circuitry
        // DAC PLL Configuration
        0x00009500, //01:bypasspll 00:en dac pll
        0x00079000, // bypass 0xFF enbale 0x00
        0x00079100, // bypass 0x1F enbale 0x00
        0x00079408, //Set DAC PLL charge pump current,The recommended setting is 0x08
        // wait 100ms
    	// fDAC = (8 x N x fREF)/M/(Register 0x094, Bits[1:0] + 1)
    	// N=4, M=1, fdac_DIV=2, fout_DIV=2(b01)
    	// refclk 300M VCO=9600, fdac=4800
        0x00079904, // N=4  // [7:6]:ADCCLKDIVIDER, [5:0]N_DIVIDER: 2~50
        0x00079318, // M=1  // [5:0]:M_DIVIDER(0~3)=M+1 // (default)0x18:[1:0]11, 0x1B:[1:0]11
        0x00009400, // DIV2 // [1]PLL_VCO_DIV3_EN; [0]PLL_VCO_DIV2_EN; (00:DAC clock= PLL VCO Freq 01:1/2 10:1/3)
        0x00079202, // Reset VCO
        // Wait 100 ms for PLL to lock,than read 7B5 back bit0=1 ensure PLL is locked
        // Delay Lock Loop (DLL) Configuration
        0x000C168,  // If fDAC is < 4.5 GHz, set this register to 0x48. Otherwise, set this register to 0x68 //**
        0x000C169,  // If fDAC is < 4.5 GHz, set this register to 0x49. Otherwise, set this register to 0x69 //**
        0x000C701,  // Enable DLL read status.
        ////read 0C3 back bit0=1 ensure DLL is locked
        // Calibration
        // JESD204B Mode Setup
        0x0010000,    //Power up digital datapath clocks when internal clocks are stable.
        // JESDMODE = {1'b1, 5'b10010},
        // MODE 18:LMFS-4112   Lane Rate =  (M/L) ? NP ? (10/8) ? Data Rate =10G
    //	0x0011032,  //bit7 can read  // mode18
    //	0x0011032,  //bit7 can read  // mode19
    //	0x0011111,  // [7:4]DP_INTERP_MODE [3:0]	CH_INTERP_MODE
    	// JESDMODE = {1'b1, 5'b01000},
        // MODE 8:LMFS-4211   Lane Rate =  (M/L) ? NP ? (10/8) ? Data Rate =12G
    	// MODE 9:LMFS-4222
    //    0x0011028,  //bit7 can read  // mode8
        0x0011029,  //bit7 can read  // mode9
        0x0011181,  // [7:4]DP_INTERP_MODE [3:0]	CH_INTERP_MODE
        0x0008400,  //SYSREF 00:ac subclass1 01:ac subclass0    //**
        0x0031200,  //Set SYNCOUTx?鍗� error duration, depending on the selected mode
    	0x0030008,  //08:double link 0
        0x0047509,  //Soft reset the JESD204B quad-byte deframer
        0x0045383,  //Descrambling is enabled,5'b00011=shijizhi -1 //**
        0x004582F,  //2f:subclass1 0f:subclass0 //NP=16 //**
        0x003000C,  //0C:double link 1
        0x0047509,  //Soft reset the JESD204B quad-byte deframer
        0x0045383,  //Descrambling is enabled,5'b00011=shijizhi -1 //**
        0x004582F,  //2f:subclass1 0f:subclass0 //NP=16 //**
        // Channel Datapath Setup: Digital Gain and Channel NCOs, CHINTERPMODE=1 skip
    	// --- GAIN ---
    	// code for each channel is 12-bit resolution.
    	// 0 <= GAIN <= (2^12-1)/12^11
    	// 閳巻鍨� dB < dBGain 閳拷 +6.018 dB
    	// Gain = Gain Code 鑴� (1/2048)
    	// dBGain = 20 鑴� log10 (Gain)
    	// Gain Code = 2048 鑴� Gain = 2^11 鑴�10^(dBGain/20)
    	// --- NCO ---
    	// fCarries / fNCO = M/N = (FTW + ACC_DELTA/ACC_MODULUS) / 2^48
    	// fNCO = fDATA 鑴� Channel Interpolation/
    	// fNCO = fDAC/Main Interpolation = fSUMMING_NODE
    	// Channel Modulus NCO Mode (Direct Digital Synthesis (DDS))
    	//     The modulus mode is enabled by programming the DDSC_MODULUS_EN bit in
    	//     the DDSC_DATAPATH_CFG register to 1 (Register 0x130, Bit 2 = 0b1).
    	// If DDSC_MODULUS_EN is low,
    	//    the main datapath NCO frequency = fDAC 鑴� (DDSC_ FTW/248).
    	// If DDSC_MODULUS_EN is high,
    	//    main datapath NCO frequency = fDAC 鑴� (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/2^48.
    	//    2^48 = 28,147,497,671,065 = 閳ワ拷0x1999_9999_9999閳ワ拷
    	// DDSC_ACC_DELTA must be > 0.
    	// --- Set ---
         0x000083F,  // [5:0]:bit[x] corresponds to the channel x datapath
         0x0014601,  // CHNLGAIN[ 7:0]
         0x0014700,  // CHNLGAIN[15:8]
         0x0013000,  // disable NCO
    //	 0x0013040,  // enable NCO
    //	 0x0013044,  // enable NCO & modulus
    	// [0]:DDSC_EN_DC_INPUT
    	//     dc test mode or NCO test mode is desired
    	//     Integer NCO mode calculation: DDSC_FTW = (fCARRIER/fNCO) x 248, where fNCO = fDATA/CH_INTERP_MODE.
    	// [2]:DDSC_MODULUS_EN
    	// [6]:DDSC_NCO_EN
    	// Fdac = 4.8G
    	// FNCO = 2.4G
    	// Fc= 1.2G FTW = 0x8000_0000_0000
         0x0013200,  // DDSCFTW[ 7: 0]
         0x0013300,  // DDSCFTW[15: 8]
         0x0013400,  // DDSCFTW[23:16]
         0x0013500,  // DDSCFTW[31:24]
         0x0013600,  // DDSCFTW[39:32]
         0x0013780,  // DDSCFTW[47:40]
         0x0013800,  // DDSCNCOPHASEOFFSET[ 7:0]
         0x0013900,  // DDSCNCOPHASEOFFSET[15:8]
         0x0013A0A,  // DDSCACCMODULUS[ 7: 0]
         0x0013B00,  // DDSCACCMODULUS[15: 8]
         0x0013C00,  // DDSCACCMODULUS[23:16]
         0x0013D00,  // DDSCACCMODULUS[31:24]
         0x0013E00,  // DDSCACCMODULUS[39:32]
         0x0013F00,  // DDSCACCMODULUS[47:40]
         0x0014000,  // DDSCACCDELTA[ 7: 0]
         0x0014100,  // DDSCACCDELTA[15: 8]
         0x0014200,  // DDSCACCDELTA[23:16]
         0x0014300,  // DDSCACCDELTA[31:24]
         0x0014400,  // DDSCACCDELTA[39:32]
         0x0014500,  // DDSCACCDELTA[47:40]
         0x0013100,  //
         0x0013101,  // 0->1:Update all NCO phase and FTW words
        // Main DAC Datapath Setup: PA Protect and Main NCOs, DPINTERPMODE =1 skip
         0x00008C0, // MAIN_DP Dual
    //	 0x0011200,// disable NCO
    //	 0x0011208,// enable NCO
    	 0x001120C,// enable NCO & Modulus
    //	 0x001120E,// enable NCO & Modulus & UPPER SIDEBAND
    //   [5:0] DDSM_MODE 00: DAC0=I0,DAC1=I1;
    //	 [3]	 Enable NCO for selected channels in paging Register 0x008.  0: disable 1: enable.
    //	 [2]	 Enable NCO modulus for selected channels in paging Register 0x008. 0: disable 1: enable.
    //	 [1]	 Select sideband from modulation result.
    //	 0b0 = upper sideband.
    //	 0b1 = lower sideband (spectral flip).
    //	 [0]    Set this bit to 0.
    //	 Integer NCO mode calculation: DDSM_FTW = (fCARRIER/fDAC) / 2^48.
    //       −fDAC/2 ≤ fCARRIER < +fDAC/2
    	 // Fdac = 4.8G 2^48=281,474,976,710,656‬=0x1_0000_0000_0000
    	 // ‭281474976710656‬
    	 // Fc= .48G FTW = 0x‭1999_9999_9999  modulus x0A delta 0x06 1/10
         // Fc= 1.5G FTW = 0x‭22AA_AAAA_AAAA.66~7
         0x00114AA,    //DDSMFTW[7:0]
         0x00115AA,    //DDSMFTW[15:8]
         0x00116AA,    //DDSMFTW[23:16]
         0x00117AA,    //DDSMFTW[31:24]
         0x00118AA,    //DDSMFTW[39:32]
         0x0011922,    //DDSMFTW[47:40]
         0x0011C00,    //DDSMNCOPHASEOFFSET[7:0]
         0x0011D00,    //DDSMNCOPHASEOFFSET[15:8]
    	 // delta / modulus
    	 // .66~7
         0x0012400,    //DDSMACCMODULUS[7:0]
         0x0012540,    //DDSMACCMODULUS[15:8]
         0x001267A,    //DDSMACCMODULUS[23:16]
         0x0012710,    //DDSMACCMODULUS[31:24]
         0x00128F3,    //DDSMACCMODULUS[39:32]
         0x001295A,    //DDSMACCMODULUS[47:40]
         0x0012AAB,    //DDSMACCDELTA[7:0]S
         0x0012B2A,    //DDSMACCDELTA[15:8]S
         0x0012CFC,    //DDSMACCDELTA[23:16]S
         0x0012D0A,    //DDSMACCDELTA[31:24]S
         0x0012EA2,    //DDSMACCDELTA[39:32]S
         0x0012F3C,    //DDSMACCDELTA[47:40]S
         0x0011301,    //0->1:loads the FTW
        // JESD204B SERDES Required Interface Setup
        0x00240AA,    //For insertion loss a?? 11 dB, set to 0xAA, otherwise, set to 0xFF
        0x00241AA,    //For insertion loss a?? 11 dB, set to 0xAA, otherwise, set to 0xFF
        0x0024255,    //For insertion loss a?? 11 dB, set to 0x55, otherwise, set to 0xFF
        0x0024355,    //For insertion loss a?? 11 dB, set to 0x55, otherwise, set to 0xFF
        0x002441F,    //EQ settings
        0x0020100,    //Power down unused PHYs, Bit x corresponds to SERDINx?鍗� pin power-down //**
        0x0020300,    //01:Powers down the SYNCOUT1?鍗� output pins //** 00: dual-link mode
        0x0025301,    //01:SYNCOUT0?鍗� is set to LVDS output 00:SYNCOUT0?鍗� is set to CMOS output //**
        0x0025401,    //01:SYNCOUT1?鍗� is set to LVDS output 00:SYNCOUT1?鍗� is set to CMOS output   //**
        0x0021016,    //SERDES required register write
        0x0020000,    //Power up the SERDES circuitry blocks.
        // wait 100ms
        0x0021086,    //SERDES required register write
        0x0028001, //Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration
        // read 281 back bit0=1 indicate the SERDSES PLL is locked
        // Transport Layer Setup, Synchronization, and Enable Links
        0x0030808,    //Crossbar setup
        0x003060C,    //If operating in Subclass 0, this register write is not needed
        0x003070C,    //If operating in Subclass 0, this register write is not needed
        0x0030400,    //If operating in Subclass 0, this register write is not needed
        0x0030500,    //If operating in Subclass 0, this register write is not needed
        0x0003A02,    //SYSREF, Set up sync for one-shot sync mode.
        0x003000B,    //01:LINK EN 0B:double link enable
    //	0x0030008,    //00: disable link
        // Cleanup Registers
        0x001DE03,    //03:Enable SPI control 00:DISABLE SPI control
        0x00008C0,    //Sets the main DAC paging
        0x005960C     //SPI turn on TXENx feature

    thanks again!