AD9162 not passing CGS on some devices

Hello.  I have a PCB design with 8 DACs (AD9162) and I occasionally have a problem establishing a link with one or more of the devices.  I have posted about this before, but I now have more details that may be helpful.

I ran a PRBS test and took a "snapshot" of a working DAC versus a non-working DAC and the results were as follows:

The transmit side is sending 0xBCBCBCBC.  Writing a ‘1’ to bit 0 of address 0x31E on the AD9162 to capture a snapshot of the received data resulted in 0x829F5829F5 for each lane on a working DAC.  This data is the snapshot that was stored in addresses 0x31F to 0x323. The non-working DAC receive data was 0xF5829F5829.

So the data in the non-working DAC appears byte shifted, but the characters are correct, suggesting that the lanes are seeing valid data on them.  Does this byte shift in the decoded data suggest a problem with the DAC or the PCB layout? 

Any help you can provide would be greatly appreciated.

Thanks so much,

John

  • 0
    •  Analog Employees 
    on Nov 1, 2021 3:53 PM

    Hello,

    I don't think the byte shift would be the cause of CGS errors and lane alignment takes place after CGS.  CGS errors are typically caused by clocking issues like slightly off frequency at one end of the link or other, signal integrity issues or possibly manufacturing issues on the pcb (bad solder joint, for example.  Here is a link to our JESD204B debug guide that may help you with the diagnosis.

    Del

  • Thanks for your input on this.  I also noticed that when the CGS test fails, register x470 reads one of two values, either x00 or xF0.  So it looks like either all of the lanes fail or the first four lanes pass, but not the next four.  Does this give any indication on where the problem could be? 

    In the meantime I will go through the JESD Debug guide to see if I can find anything.

    Thank you,

    John