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ad9164 sync never goes high

I try to use the jesd204b ip core to communacate with ad9164 in the old pcb board,there is a xc7k325tffg900-2 and an ad9164.This board works well with another program that the jesd204b interface is write by someone else.There is no sysref signal be connected to the dac ,so I have to use subclass0.
The dac SampleRate is 2.5Gsps with 8 lanes,so the LaneRate is 20*2.5G/8=6.25G,
and the core clock is 6.25/40=156.25MHz(refer xilinx pg066 ,page 48 "The core clock always runs at the required rate (1/40th of the serial line rate").We can get the clock information from the follow picture :

About how to configure the dac,I refer setting:
//register configure value:
    //dac_r0 to dac_r15 is discreped in :Table 42. Configure DAC Start-Up Sequence After Power-Up
    localparam dac_r0 ={8'h00,1'b0,15'h000,8'h18};        
    localparam dac_r1 ={8'h00,1'b1,15'h000,8'h18};          
    localparam dac_r2 ={8'h00,1'b0,15'h0d2,8'h52};        
    localparam dac_r3 ={8'h00,1'b0,15'h0d2,8'hd2};        
    localparam dac_r4 ={8'h00,1'b0,15'h606,8'h02};        
    localparam dac_r5 ={8'h00,1'b0,15'h607,8'h00};        
    localparam dac_r6 ={8'h00,1'b0,15'h604,8'h01};        
    localparam dac_r7  ={8'h00,1'b1,15'h003,8'h00};       
    localparam dac_r8  ={8'h00,1'b1,15'h004,8'h00};       
    localparam dac_r9  ={8'h00,1'b1,15'h005,8'h00};       
    localparam dac_r0A ={8'h00,1'b1,15'h006,8'h00};       
    localparam dac_r0B ={8'h00,1'b1,15'h604,8'b0000_0010};
    localparam dac_r0C ={8'h00,1'b0,15'h058,8'h03};       
    localparam dac_r0D ={8'h00,1'b0,15'h090,8'h1E};       
    localparam dac_r0E ={8'h00,1'b0,15'h080,8'h00};       
    localparam dac_r0F ={8'h00,1'b0,15'h040,8'h00};        
    localparam dac_r10 ={8'h00,1'b0,15'h020,8'h0F};        
    localparam dac_r11 ={8'h00,1'b0,15'h09E,8'h85};        
    localparam dac_r12 ={8'h00,1'b0,15'h091,8'hE9};
    localparam dac_r13 ={8'h00,1'b1,15'h092,8'b0000_0001};
    localparam dac_r14={8'h00,1'b0,15'h0E8,8'h20};
    localparam dac_r15={8'h00,1'b0,15'h152,8'h00};//end of config
    //register for config of jesd204b Table 43
    localparam dac_r16={8'h00,1'b0,15'h300,8'h00};//Ensure the SERDES links are disabled before configuring them.
    localparam dac_r17={8'h00,1'b0,15'h4B8,8'hFF};//Enable JESD204B interrupts
    localparam dac_r18={8'h00,1'b0,15'h4B9,8'h01};//Enable JESD204B interrupts  
    localparam dac_r19={8'h00,1'b0,15'h480,8'h38};//Enable SERDES error counters       
    localparam dac_r1A={8'h00,1'b0,15'h481,8'h38};//Enable SERDES error counters       
    localparam dac_r1B={8'h00,1'b0,15'h482,8'h38};//Enable SERDES error counters         
    localparam dac_r1C={8'h00,1'b0,15'h483,8'h38};//Enable SERDES error counters       
    localparam dac_r1D={8'h00,1'b0,15'h484,8'h38};//Enable SERDES error counters       
    localparam dac_r1E={8'h00,1'b0,15'h485,8'h38};//Enable SERDES error counters       
    localparam dac_r1F={8'h00,1'b0,15'h486,8'h38};//Enable SERDES error counters       
    localparam dac_r20={8'h00,1'b0,15'h487,8'h38};//Enable SERDES error counters       
    localparam dac_r21={8'h00,1'b0,15'h110,8'h80};//Configure number of lanes (Bits[7:4]) and interpolation rate (Bits[3:0]).       
    localparam dac_r22={8'h00,1'b0,15'h111,8'h00};//Configure the datapath options for Bit 7 (INVSINC_EN)...
    localparam dac_r23={8'h00,1'b0,15'h230,8'h00};//Configure the CDR block according to Table 19 for both half rate enable and the divider
    localparam dac_r24={8'h00,1'b0,15'h289,8'h00};//Set up the SERDES PLL divider based on the conditions shown in Table 18
    localparam dac_r25={8'h00,1'b0,15'h084,8'h00};//Set up the PLL reference clock rate based on the conditions shown in Table 18.
    localparam dac_r26={8'h00,1'b0,15'h200,8'h00};//Enable JESD204B block (disable master SERDES power-down)
    //311 312 313 all zero in ldx code
    localparam dac_r27={8'h00,1'b0,15'h475,8'h09};//Soft reset the JESD204B quad-byte deframer
    //476 477
    localparam dac_r28={8'h00,1'b0,15'h450,8'h00};//DID
    localparam dac_r29={8'h00,1'b0,15'h451,8'h00};//BID
    localparam dac_r2A={8'h00,1'b0,15'h452,8'h00};//ADJDIR    PHADJ    LID0
    localparam dac_r2B={8'h00,1'b0,15'h453,8'h07};//SCR        L-1
    localparam dac_r2C={8'h00,1'b0,15'h454,8'h00};//F-1
    localparam dac_r2D={8'h00,1'b0,15'h455,8'h1F};//K-1
    localparam dac_r2E={8'h00,1'b0,15'h456,8'h00};//M-1
    localparam dac_r2F={8'h00,1'b0,15'h457,8'h0F};//CS    N-1
    localparam dac_r30={8'h00,1'b0,15'h458,8'h0F};//SUBCLASSV    NP-1
    localparam dac_r31={8'h00,1'b0,15'h459,8'h23};//JESDV    S-1
    localparam dac_r32={8'h00,1'b0,15'h45A,8'h80};//HD    CF
    localparam dac_r33={8'h00,1'b0,15'h45B,8'h00};//RES1
    localparam dac_r34={8'h00,1'b0,15'h45C,8'h00};//RES2
    localparam dac_r35={8'h00,1'b0,15'h45D,8'h49};//check sum0x49//in lxd code is : 67 66
    localparam dac_r36={8'h00,1'b0,15'h475,8'h01};//Bring the JESD204B quad-byte deframer out of reset
    localparam dac_r37={8'h00,1'b0,15'h201,8'h00};//Set any bits to 1 to power down the appropriate physical lane
    localparam dac_r38={8'h00,1'b0,15'h2A7,8'h01};//(Optional) Calibrate SERDES PHY Termination Block 1 (PHY 0, PHY 1, PHY 6, PHY 7)
    localparam dac_r39={8'h00,1'b0,15'h2AE,8'h01};//(Optional) Calibrate SERDES PHY Termination Block 2 (PHY 2, PHY 3, PHY 4, PHY 5)
    localparam dac_r3A={8'h00,1'b0,15'h29E,8'h1F};//Override defaults in the SERDES PLL settings (private)
    localparam dac_r3B={8'h00,1'b0,15'h206,8'h00};//Reset  the CDR
    localparam dac_r3C={8'h00,1'b0,15'h206,8'h01};//Enable the CDR
    localparam dac_r3D={8'h00,1'b0,15'h280,8'h01};//Enable the SERDES PLL
    localparam dac_r3E={8'h00,1'b1,15'h281,8'h01};//***Read back Register 0x281 until Bit 0 = 1 to indicate the SERDES PLL is locked
    localparam dac_r3F={8'h00,1'b0,15'h300,8'h01};//Enable SERDES links (begin bringing up the link)
    localparam dac_r40={8'h00,1'b0,15'h206,8'h00};//Reset  the CDR
    localparam dac_r41={8'h00,1'b0,15'h206,8'h01};//Enable the CDR
    localparam dac_r42={8'h00,1'b0,15'h280,8'h01};//Enable the SERDES PLL
    localparam dac_r43={8'h00,1'b1,15'h470,8'hFF};//***Read the CGS status for all lanes
    localparam dac_r44={8'h00,1'b1,15'h471,8'hFF};//***Read the frame sync status for all lanes
    localparam dac_r45={8'h00,1'b1,15'h472,8'hFF};//***Read the good checksum status for all lanes
    localparam dac_r46={8'h00,1'b1,15'h473,8'hFF};//***Read the initial lane sync status for all lanes
    localparam dac_r47={8'h00,1'b0,15'h024,8'h1F};//Clear the interrupts
    localparam dac_r48={8'h00,1'b0,15'h4BA,8'hFF};//Clear the SERDES interrupts
    localparam dac_r49={8'h00,1'b0,15'h4BB,8'h01};//Clear the SERDES interrupt
    localparam dac_r4A={8'h00,1'b0,15'h020,8'h0F};//optional. Enalbe the interrupts
    localparam dac_r4B={8'h00,1'b0,15'h4B8,8'hFF};//optional. Enalbe JESD204B interrupts
    localparam dac_r4C={8'h00,1'b0,15'h4B9,8'h01};//optional. Enalbe JESD204B interrupts

You can get my setting from the checksum picture:

When I power up the board , the spi configure got stuck in  reading register:0x471,its value is 0x00,not 0xFF ! From the datasheet I can know there is problem about the initial frame synchronization,but why ? I try to find the reason by myself,but 4 days passed,I have read a lot of datasheets and posts from EngineerZone,I still got stuck.If you have any suggest ,please tell me,thanks advance.