AD9106 / AD9102 - Dout

I represented when we would expect the end of Dout by arrow.

Best regards,

Marc

Hello,

Try changing the DOUT_START_DELAY register value. Here are the registers related to DOUT. Default value is the minimum register value.



More details about DOUT in page 27 of the datasheet.

Regards,
Shine

Hello,

Try changing the DOUT_START_DELAY register value. Here are the registers related to DOUT. Default value is the minimum register value.



More details about DOUT in page 27 of the datasheet.

Regards,
Shine

Hello Shine,

Yes, we can set a delay with this register but we want to reduce the duration of the DOUT.

Please try changing the value of the DOUT_STOP bits in the DOUT_CONFIG register.

Hello Shine !

This register slightly increases the duration of Dout (as expected) but still not what we need.

The pattern generator seems to turn off a long time after the pattern end.

Do you have a screenshot where the Dout signal last exactly the duration of the pattern ?

Best regards,

Marc

Hello Marc38,

Hope you are safe and well. 

Have you tried adjusting the PATTERN_PERIOD? It should be equal to the number of SRAM addresses used for the waveform multiplied by clock period.

You can also try raising the edge of the trigger pin or writing  0 to RUN bit 0x1E [0]. The  pattern generation only stops at the end of the current pattern period.

Thanks, 

Lorenz

Hello Lorenz,

I took screenshots to get Dout signal duration when the pattern period equals to 4096.

Almost 7ms ! while the useful signal lasts only for ~30 µs

And when the pattern period equals 2048. About 3.5ms.

Now with a zoom on the signal:

PATTERN_PERIOD = 4096

PATTERN_PERIOD = 2048

This register reduces the duration of Dout but it is still far too long.

Here are the registers values:

a1 E00
a2 0
a3 10
a4 0
a5 0
a6 0
a7 0
a8 0
a9 1F0A
aA 1F0A
aB 1F0A
aC 1F0A
aD 0
aE 4000
aF 0
a10 0
a11 0
a12 0
a13 0
a14 0
a15 0
a16 0
a17 0
a18 0
a19 0
a1A 0
a1B 0
a1C 0
a1D 0
a1E 1
a1F 1
a20 E
a21 0
a22 0
a23 0
a24 0
a25 0
a26 101
a27 0
a28 111
a29 1000
a2A 101
a2B 1
a2C 3
a2D 0
a2E 0
a2F 0
a30 0
a31 0
a32 0
a33 0
a34 0
a35 7FF0
a36 1
a37 200
a38 0
a39 0
a3A 0
a3B 0
a3C 0
a3D 0
a3E 0
a3F 0
a40 0
a41 0
a42 0
a43 0
a44 0
a45 0
a46 0
a47 0
a48 0
a49 0
a4A 0
a4B 0
a4C 0
a4D 0
a4E 0
a4F 0
a50 0
a51 FFF0
a52 FFF0
a53 100
a54 0
a55 FFF0
a56 FFF0
a57 100
a58 0
a59 FFF0
a5A FFF0
a5B 100
a5C 0
a5D 0
a5E FFF0
a5F 100
a60 0
a61 0
a62 0
a63 0
a64 0
a65 0
a66 0
a67 0
a68 0
a69 0
a6A 0
a6B 0
a6C 0
a6D 0
a6E 0
a6F 0
a70 0
a71 0
a72 0
a73 0
a74 0
a75 0
a76 0
a77 0
a78 0
a79 0
a7A 0
a7B 0
a7C 0
a7D 0
a7E 0

Thank you  for addressing Marc's concern.


Hi Marc38,

Lorenz' suggestions are all correct. We just forgot to emphasize that if you want DOUT to depend on DOUT_START and DOUT_STOP values, DOUT_MODE bit should be 1. Otherwise, DOUT will be controlled manually and it will wait for DOUT_VAL bit to be toggled before it changes state. In your waveform captures, the time that DOUT changed state might be right before the next pattern period is played hence the long duration.

Moreover, you are showing channel 1 output right? If yes, the readback values of registers related to channel 1 are as follows:
0x29 PAT_PERIOD:     0x1000 - 4096 clock cycles
0x45 DDSx_CONFIG:  0x0000 - bit 2 DDS_MSB_EN1 is 0 hence SRAM address is incremented every DAC clock cycle
0x5D START_ADDR1: 0x0000 - DAC1 starts to read waveform from SRAM address 0x6000
0x5E STOP_ADDR1:   0xFFF0 - DAC1 stops to read waveform at SRAM address 0x6FFF

This means that the pattern repeats every 4096*clock period (seconds) and the DDS waveform is modulated by the values stored across all the SRAM addresses. So when you repeat the pattern, there are flat parts aside from the "useful" signal. This is because if you are using example 5 SRAM vector, only ~30us ÷ your DAC clock period SRAM addresses are non-zero. See config.h.

So if you want only the non-zero part of the signal to repeat, follow Lorenz' recommendation with regards to the START_ADDR, STOP_ADDR, and PAT_PERIOD registers.


Regards,
Shine

Hello Shine,

Thank you very much for your help.

So concerning DOUT, I disabled Dout Mode to be able to read the registers since Dout is mutiplexed with SDO. This is why you saw it disabled in the registers.

Here is what I do to enable/disable DoutMode:

void AD910xDoutMode(Uint16 state) // Ok?
{
	writeDDS(PAT_STATUS, 0);
	// Enabling Dout implies to switch to SPI3WIRE
	ShallowSPIConfig.bits.SPI3WIRE = state&1;
	ShallowSPIConfig.bits.SPI3WIREM = state&1;
	ShallowSPIConfig.bits.SPI_DRV = state&1;
	ShallowSPIConfig.bits.SPI_DRVM = state&1;
	ShallowSPIConfig.bits.DOUT_EN = state&1;
	ShallowSPIConfig.bits.DOUT_ENM = state&1;
	writeDDS(SPICONFIG, ShallowSPIConfig.all);

	writeDDS(RAMUPDATE, 1);    // update RAM
	writeDDS(PAT_STATUS, 1);

	DELAY_US(10);

	writeDDS(PAT_STATUS, 0);
	ShallowDoutConfig.bits.DOUT_MODE = state&1;
	writeDDS(DOUT_CONFIG, ShallowDoutConfig.all);

	writeDDS(RAMUPDATE, 1);    // update RAM
	writeDDS(PAT_STATUS, 1);
}

Strangely I have to do this twice to get Dout working.

Then I can change DoutStartDelay or DoutStopDelay which has an effect. I don't think it is in manual mode.

Does the start and stop delay work in manual mode too ?

Concerning PAT_PERIOD and START_ADDR, STOP_ADDR, I not sure to fully understand what you mean : PAT_PERIOD = 4096 and START_ADDR = 0x0, STOP_ADDR  = 0xFFF so it is seems consistent to me.

ShineC said:

This means that the pattern repeats every 4096*clock period (seconds) and the DDS waveform is modulated by the values stored across all the SRAM addresses. So when you repeat the pattern, there are flat parts aside from the "useful" signal. This is because if you are using example 5 SRAM vector, only ~30us ÷ your DAC clock period SRAM addresses are non-zero. See config.h.

The DDS is not used here, and there is not modulation by SRAM, I send the data in RAM directly. Here you can see with a parabolic curve repeated 4 times:

Honestly, everything else works very well including DDS (sine) mode. Only Dout is too long.

Do you have a complete list of registers with the use of Dout so I can try to match them on my board ?

Hi Marc,

Marc38 said:

Strangely I have to do this twice to get Dout working.

You need to write on the PAT_STATUS bit first before setting the RAMUPDATE bit. Maybe that's why you need to go through your code twice to enable DOUT.

Marc38 said:

Does the start and stop delay work in manual mode too ?

No.

ShineC said:

Otherwise, DOUT will be controlled manually and it will wait for DOUT_VAL bit to be toggled before it changes state.

Marc38 said:

Do you have a complete list of registers with the use of Dout so I can try to match them on my board ?

Unfortunately we only have code for 4-wire SPI mode.

In the waveform you sent below, you're using all 4096 SRAM addresses?

Marc38 said:

The DDS is not used here, and there is not modulation by SRAM, I send the data in RAM directly. Here you can see with a parabolic curve repeated 4 times:

Regards,
Shine

Hello Shine,

Yes the signals were using all 4096 SRAM addresses in the screenshots. And we are only using the channel 1.

So we read as much points as in PATTERN PERIOD.

Only Dout is too long now. I can update the registers correctly immediately now.

Let me know if you have any suggestion.

Regards,

Marc

Hello,

Do you have any new idea to try ?

This problem prevents us from using the component on our new product which is unfortunate since it covers  all the other needs.

Best regards,

Marc