AD9162 does not achieve CGS anymore

Hello.  I have designed a system that uses multiple AD9162 devices and one of the devices no longer passes the CGS stage.  This device was working fine, but then started failing in the CGS stage.  I have checked all of the power supplies and clocks and SYSREFs going to the devices, everything looks ok.  I was able to compare the bad device boot sequence to a know good device boot sequence and the results are listed below.

All register readings matched with the exception of the following:

REG ADDR | GOOD DEVICE| BAD DEVICE

0x092 | 0x01 | 0x03 (This value did clear to a 0x01 and remained that way from that point on, so I think it's ok)

0x034 | 0x24 | 0x14

0x302 | 0x07 | 0x00

0x470 | 0xFF | 0x00 (This is where CGS fails, I did not go any further)

I am using a total of 64 AD9162 devices (8 devices on 8 different PCBs) and a total of approximately 5 or 6 of them have this same issue.  Any help would be much appreciated.Thank you,

John

Parents
  • 0
    •  Analog Employees 
    on Aug 13, 2021 1:53 PM

    CGS failures are typically (90%) caused by clocking issues on one side of the link or the other.  Ensue you are providing the exact reference clock needed for the lane rates you are expecting.  Also check the signal level and signal integrity of the clocks.  Also, is SYNCOUT always low or is it toggling?

  • Hello Del.  Did you have a chance to review my submission regarding the PRBS test? 

    See below:

    I ran a "snapshot" test of a working DAC versus a non-working DAC and the results were as follows:

    The transmit side is sending 0xBCBCBCBC.  Writing a ‘1’ to bit 0 of address 0x31E on the AD9162 to capture a snapshot of the received data resulted in 0x829F5829F5 for each lane on a working DAC.  This data is the snapshot that was stored in addresses 0x31F to 0x323. The non-working DAC receive data was 0xF5829F5829.

    So the data in the non-working DAC appears byte shifted, but the characters are correct, suggesting that the lanes are seeing valid data on them.

    Hopefully this is helpful information for you.

    Thanks so much,

    John

Reply
  • Hello Del.  Did you have a chance to review my submission regarding the PRBS test? 

    See below:

    I ran a "snapshot" test of a working DAC versus a non-working DAC and the results were as follows:

    The transmit side is sending 0xBCBCBCBC.  Writing a ‘1’ to bit 0 of address 0x31E on the AD9162 to capture a snapshot of the received data resulted in 0x829F5829F5 for each lane on a working DAC.  This data is the snapshot that was stored in addresses 0x31F to 0x323. The non-working DAC receive data was 0xF5829F5829.

    So the data in the non-working DAC appears byte shifted, but the characters are correct, suggesting that the lanes are seeing valid data on them.

    Hopefully this is helpful information for you.

    Thanks so much,

    John

Children
No Data