Hello, I am debugging on AD9163 of the custom board.
The DAC device clock is 4.8G and jesd204b is 8 lane with 4G lane rate.
Other configration was as followed:
0x110=0x84 // 8lane and 6 interpolar
0x230=0x0 //lane rate less than 6G
0x289=0x01 //ref clk div by 2
0x084=0x00 // pll ref clk rate 1x
After the start up sequence, the 0x092 was 0x0(dll unlocked), the 0x281 was 0x0B(pll locked).
Has some one know the source of this issue?
