AD9173 DLL lock fail

Hello,

We are currently working on the evaluation board AD9173-FMC-EBZ, this one is interfaced via the FMC connector with evaluation board AC701 (Artix 7 with GTP).

Following the "startup séquence" described on page 66 to 72 of the Datasheet (in order Table 49 -> Table 50->Table 51), the PLL of the DAC locks (register 0x7B5 bit 0) but the DLL never locks (register 0x0C3 bit 0) .

The DAC has the following configuration:
CLKIN = 200 MHz
Internal PLL = ON (M_DIVIDER=1, N_DIVIDER=6, PLL_VCO_DIV=2) so CLKDAC = 4.8GS/s
Channel interpolation = 6
Datapath interpolation = 8
Data Rate = 100 MS/s
Lane Rate = 4 Gbit/s
SYSREF = 25MHz
JESD204B mode = mode 0

All power supplies on the evaluation board have been checked, and meet the datasheet specifications.

The levels of the clocks and Serdes have also been checked, and respect the specifications.

Short Resume:
Internal PLL is LOCKED (register 0x7B5 bit 0)
DLL is not LOCKED ERROR (register 0x0C3 bit 0)
Serdes PLL is LOCKED (register 0x281 bit 0)

Do you have any research to unblock me? Is it normal that the PLL of SERDES is locked but not the DLL?

Thank you very much

Regards


Romain