DAC AD9173 Infernal Loop Back Test

Hello,
We are currently working on the evaluation of the AD9173 DAC, for that we use the AD9173-FMC-EBZ evaluation board alone (WITHOUT OS).
This board is powered via a laboratory power supply (12V 3A).
After having successfully passed the DC test Tone, I would like to test the JESD physical layer of the DAC. For that I followed the procedure described on the Datasheet (p44) which is called "Infernal Loop Back Test", but nothing seems to work.

Below is the list of registers programmed to perform an "Infernal Loop Back Test", PN7 lane 0:

All registers remain at 0x00 ... and bit 0 of register 0x31D never changes state : ( below the UART output)

Do you have a research lead/ a detailed process?
Thanking you for your help
Romain

  • 0
    •  Analog Employees 
    on May 17, 2021 2:37 PM

    Hi Romain, 

    Just to make sure, there is an additional step #6 that walks through how to configure the PRBS receiver.

    Please note that in the AD9174/5/6 datasheets the procedure was modified slightly, mainly for clarity. It may help in this case. Please see the PRBS Testing section in AD9176 (Rev. B) (analog.com). "internal loop back" == "internal PRBS7 generator"

    Please note that an external 12V should not be used when the board is plugged into a dev kit using the FMC connector... Hopefully this is not related to the issue you are seeing! 

    Landsman  

  • Landsman,
    Thank you for your responsiveness,
    I have already taken into account step #6, for the programming of the PRBS receiver registers.
    I have just checked all the registers, via the datasheet of the AD9176, all seem to be correct, can you explain me a little more precisely the threshold set in register 0x317-0x319 (the datasheet is very succinct)?

    New UART output:

    REG 0x31D: status register for each channel, this register must be set to 0xFF (bit 0 to 1) when the PRBS test passes on channel 0 but remains in a failed state....

    Thanks

    Romain

  • 0
    •  Analog Employees 
    on May 17, 2021 7:00 PM in reply to RomG

    Hi Romain,

    So looks like the UART returned non-zero values? this seems like a good sign.  

    0x317-0x319 is a 24bit error count threshold. Once the error count reaches this value the test is flagged as "failed". you could set it to 0x1 for example. 

    Regarding 0x31d, we have the following description in step #9a. Also #9b mentions the error counter (accessed through a state machine on a per-lane basis):

    I am a little unclear on the comment, but seems to me it suggests that one would write 0xFF to reset the pass/fail register.

    Please note that pass=0 and fail=1. hence the comment to force a failure first, to confirm the receiver is configure properly. 

    Landsman

  • Landsman,

    I thank you for all these precisions, when I force the generator of PRBS in reset I have well the register 0x31D = 0xFF (as specify in the datasheet).

    UART output when RESET:

    But as soon as I activate the internal PRBS generator on Lane 0, register 0x31D goes to 0xFE, bit 0 of this register remains at 0, indicating "fail test" (0 = fail, 1= pass).

    UART output:

    We can clearly see that the error counter ( 0x31A -0x31B-0x31C) is incrementing and that the test is failing... but i not understand why... 

    Thanks 

    Romain

  • 0
    •  Analog Employees 
    on May 18, 2021 10:30 PM in reply to RomG

    Hi Romain, 

    If this is using the internal PRBS7 and the PRBS receiver was configured for a PRBS7 pattern, it should not fail. 

    Do you see this on more than one board? 

    Can you generate a PRBS7 (or 15, 31) from an FPGA and do the test across an FMC connector? 

    I am guessing there is a configuration error. or possibly a supply issue on that particular board. I cannot think of anything inside the AD9173 that could lead to a failure of the internal PRBS7.

    A few other data points to check, for debug..

    does it always fail on the same logical lane?

    does it improve if the clock rate is reduced? 

    Landsman