We are currently working on the evaluation of the AD9173 DAC, for that we use the AD9173-FMC-EBZ evaluation board alone (WITHOUT OS).
This board is powered via a laboratory power supply (12V 3A).
After having successfully passed the DC test Tone, I would like to test the JESD physical layer of the DAC. For that I followed the procedure described on the Datasheet (p44) which is called "Infernal Loop Back Test", but nothing seems to work.
Below is the list of registers programmed to perform an "Infernal Loop Back Test", PN7 lane 0:
All registers remain at 0x00 ... and bit 0 of register 0x31D never changes state : ( below the UART output)
Do you have a research lead/ a detailed process?
Thanking you for your help