Error testing high bandwidth modes of ad9174-ebz

I have an ad9174-ebz board connected to an ads8-v1 pattern generator for testing.

Using supplied software (DPGDownloader and ACE), I can use several JESD modes (e.g. those labelled 00, 01, 02) quite effectively 

However I'm currently interested in testing the high instantaneous bandwidth modes, that aren't limited by the channelizer's max of 1.5GSPS.  E.g. mode "10"  (3SPS data rate, single DAC, 16-bit) and "22" (2SPS data rate, dual dac, 12-bit).

Below I've shown a screen shot of attempting to use the wizard to apply these settings to the ad9174, resulting in a pop-up "transaction error" message. After this, ACE requires a restart in order to change back to a working mode. On cicking "read SERDES status", the feedback is that the DAC PLL is not locked.  I am hoping to use the on-chip PLL default reference (ie. nothing not included in the evaluation boards). Perhaps I'm being naive here.

The results attempting to use mode 22 are identical.

Hopefully I'm doing something obviously silly. I'm using the latest version of ACE: 1.22.3063

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  • I was indeed being silly.  The input data rate needs to be an integer multiple of the reference clock for the PLL to lock.

  • 0
    •  Analog Employees 
    on Jun 16, 2021 4:00 PM in reply to morganh

    Hi morganh,

    Yes, this is partially true - the DAC rate (Fdac) that must be int-mult of 122.88.   

    The board uses a 122.88MHz XTAL to lock HMC7044 to an external reference. The HMC7044 then generates the FPGA ref clock (=lanerate/40), SYSREF, and the AD917x ref clock. The HMC7044 max VCO frequency is ~3.2GHz, which sets the upper limit.

    We are using the HMC7044 as an integer-PLL, so its VCO frequency must be int-mult of 122.88 for PLL1 and PLL2 to lock. The internal PLL of the AD917x is also integer-PLL, and so Fdac should be int-mult of 122.88 as well.

    Regarding datarate, since datarate = Fdac / interpolation, you can probably find interpolation rates that would result in a datarate that isn't 122.88 multiple. As long as Fdac is 122.88 int-mult it should be ok.

    Also, there are dividers along the clock tree, both in the HMC7044 and the AD9174, which could allow a little more flexibility for Fdac as well. 

    But the easiest in ACE would be to set the datarate = N * 122.88. 

    Landsman  

Reply
  • 0
    •  Analog Employees 
    on Jun 16, 2021 4:00 PM in reply to morganh

    Hi morganh,

    Yes, this is partially true - the DAC rate (Fdac) that must be int-mult of 122.88.   

    The board uses a 122.88MHz XTAL to lock HMC7044 to an external reference. The HMC7044 then generates the FPGA ref clock (=lanerate/40), SYSREF, and the AD917x ref clock. The HMC7044 max VCO frequency is ~3.2GHz, which sets the upper limit.

    We are using the HMC7044 as an integer-PLL, so its VCO frequency must be int-mult of 122.88 for PLL1 and PLL2 to lock. The internal PLL of the AD917x is also integer-PLL, and so Fdac should be int-mult of 122.88 as well.

    Regarding datarate, since datarate = Fdac / interpolation, you can probably find interpolation rates that would result in a datarate that isn't 122.88 multiple. As long as Fdac is 122.88 int-mult it should be ok.

    Also, there are dividers along the clock tree, both in the HMC7044 and the AD9174, which could allow a little more flexibility for Fdac as well. 

    But the easiest in ACE would be to set the datarate = N * 122.88. 

    Landsman  

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