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AD9154 configure problem

Hello!

I use AD9154 in JESD mode 4, LMFS=4211, two links, 2x interpolation, the samplerate is 1536Mhz, fref is 384Mhz. According to EXAMPLE START-UP SEQUENCE , I configure the registers. Now the serdes PLL and dac PLL is locked .I set 0X450 to 0X47D as mode 4 each link respectively and read them correctly , but I read the registers 0x400 to 0x40C from the dac, it turns out all the results are 0.What should I do to make registers 0x400 to 0x40C to be updated as registers 0X450 to 0X47D?

For your information, I read the 0x468 and it shows that disparity error. Also I observed the  ILA state in vivado, and SYNC usually pull down, the CGS and ILAS procedure is repeatedly show up.Similarly the register 0x470 is not equal to 0x0F, it seemly not stable, might be 0x0d or ox0e and so on.

So it's really thankful and generous that if anybody can give me some information about configuration.Thanks to your guys!

  • Today I change my design to example design, the link configuration is completely same but just the sample rate is different. The example design on 78 page is 1467.56 MHz but my design is 1536 MHz. The DAC  in example design is working normal and the sync signal is always high, the registers read back from the chip is correct and the output is correct. Due to the difference of sample rate , in my design  I configure:

    Register 0X08B = 0X11

    Register 0X1B6 = 0X49

    Register 0X1BB = 0X15

    Register 0X1B4 = 0X60

    The rest of registers are completely same as example design. I read back register:

    Register 0X084 = 0X22  –>    DAC PLL locked 

    Register 0x281 = 0x0B   -->    SERDES PLL locked 
    It seems that my configuration of PLLs is correct, But DAC tells me that disparity error and sync is usually down. So could your guys give me some advice about my puzzles ? Thank you !
  • Hi , 

     You can download the ACE software,  add the AD9154 by off shore (without evb bench connected with PC),  configure the chip, and save out configuration file by Marco tool. 

       by the way, you can try the FPGA  serdes loop back test first to confirm the FPGA JTX is correctly working, then connect with DAC.   also pls try the register 0x8B = 0x01 by your case.