I use AD9154 in JESD mode 4, LMFS=4211, two links, 2x interpolation, the samplerate is 1536Mhz, fref is 384Mhz. According to EXAMPLE START-UP SEQUENCE , I configure the registers. Now the serdes PLL and dac PLL is locked .I set 0X450 to 0X47D as mode 4 each link respectively and read them correctly , but I read the registers 0x400 to 0x40C from the dac, it turns out all the results are 0.What should I do to make registers 0x400 to 0x40C to be updated as registers 0X450 to 0X47D?
For your information, I read the 0x468 and it shows that disparity error. Also I observed the ILA state in vivado, and SYNC usually pull down, the CGS and ILAS procedure is repeatedly show up.Similarly the register 0x470 is not equal to 0x0F, it seemly not stable, might be 0x0d or ox0e and so on.
So it's really thankful and generous that if anybody can give me some information about configuration.Thanks to your guys!