My DAC requirements are
1. Single link mode
2. L : 8
3. M : 2
4. F : 1
5. S : 2
6. NP : 16
7. N : 16
8. K : 32
9 HD :1
10. SUBCLASS 1
My sampling frequency is 2.94912 GHz . From this i have calculated the Lane rate i.e. 14.7456Gbps .
datapath interpolation and main path interpolation are (x1) . I am Using Ultra scale FPGA which consists GTH transceiver of 16.3 Gbps lane rate capability.
i am using Direct clock source insted of internal PLL.
I have dought in my JESD mode selection and what are the registers to configure for the JESD communication.
From start up sequence i have followed
1. power up sequence
2. DAC PLL configuration first three registers
--> 0x095 -- 0x01
--> 0x790 -- 0xFF
--> 0x791 -- 0xFF
3. JESD Mode set up registers for single link.
4. JESD SERDES Required interface setup.
5. Transport layer setup.
i have chacked the 0x281 for SERDES PLL lock . the read data is 0x01.
is this configuration is enough for JESD communication...?
When the SYNCOUT will be generated from DAC ....?
