AD9164 Register settings

I am trying to setup the AD9164 board from scratch.

I made a following setting sequence refering to start up sequence,

but didn't go well.

And 2nd step , 
I tried to check address 0x31E PHY_DATA_SNAPSHOT function,

but the snapped data is always 0x00.

I checked the serdes input lane by oscilloscope , 
the somthing signal was comming . but no validation checked.

I think irresponsible value was snapped if the input signal is wrong. 

Would you help me if these setting is ok ?

Thanks.

------------------------------------------------------

<1st settings>

#-------------------------------------
# Fdac=3200M
# L=8/Interpolate=16
# LaneRate=1Gbps

# SYSREF CLK  is not inputted.(always 0)
#-------------------------------------

w,0000,18
w,00D2,52
w,00D2,D2
w,0606,02
w,0607,00
w,0604,01
r,0003     --->  0x04
r,0004     --->  0x64
r,0005     --->  0x91
r,0006     ----> 0x03
r,0604      ----> 0x52
w,0058,03
w,0090,1E
w,0080,00
w,0040,00
w,0020,0F
w,009E,85
w,0091,E9
#--0092: DLL Status
r,0092          ----> 0x01
w,00E8,20
w,0152,00
#---------------------------------------
# JESD setings
# 1Gbps: 0x084[5:4]=01/0x289[1:0]=10
#---------------------------------------
w,0300,00
w,04B8,FF
w,04B9,01
w,0480,38
w,0481,38
w,0482,38
w,0483,38
w,0484,38
w,0485,38
w,0486,38
w,0487,38
#-- 0x0334: Lane Invert
w,0334,F0
#-- 0x0110: Lane/Interpolate
w,0110,87
w,0111,00
w,0230,04
w,0289,02
w,0084,10
w,0200,00
#--0x475(3): QBD reset on
w,0475,09
#-- 0x0453(7): Descramble off
w,0453,00
w,0458,00
w,0459,20
#--0x475(3): QBD reset off
w,0475,01
w,0201,00
w,02A7,01
w,02AE,01
w,029E,1F
#-- 0x0206: CDR
w,0206,00
w,0206,01
#-- 0x0280: Serdes PLL
w,0280,01
#--0281: PLL Status
r,0281             ---> 0x0b
#--0300: Enable Serdes
w,0300,01
r,0470      ----> 0x00
r,0471      ----> 0x00
r,0472      ----> 0x00
r,0473      ----> 0x00
-------------------------------------------

<2nd settings>

#--0092: DLL Status
r,0092            ---> 0x01
#--0281: PLL Lock
r,0281            ----> 0x1b
#--0200: MSTER PowerDown
r,0200             ----> 0x00
#--0201: PHY PowerDown
r,0201              ----> 0x00
#--
r,02AC              ----> 0x0a
w,02A8,1E
r,02A8                ----> 0x1e
r,02B3                ----> 0x0a
#--Lane0 termination val
r,02BB                -----> 0x00
#--Lane1 termination val
r,02BC                 ----> 0x00
#--Lane2 termination val
r,02BD                 ----> 0x00
#--Lane3 termination val
r,02BE                 ----> 0x00
#--Lane4 termination val
r,02BF                 ----> 0x00
#--Lane5 termination val
r,02C0                 ----> 0x00
#--grab phy recv data
w,031E,1D
w,031E,1C
r,031F    ----> 0x00
r,0320   ----> 0x00
r,0321   ----> 0x00
r,0322   ----> 0x00
r,0323   ----> 0x00

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