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AD9744

Hello, 

     The Data sheet of AD9744 clock input section :“ In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of the CLK+ and CLK- inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p
 ” 

     LVDS swing is 350MVp-p, does this DAC support LVDS clock input?

     Thanks!

  • Hello,

    Thanks for your query. I have asked my colleague, FormerMember to research and reply.  Please give him a couple of days to do so.

    Regards,

    Del

    • Hello, do you have the results now?

  • Hi,

    Sorry for the delay. Unfortunately, you can't source the clock with an LVDS clock. The differential swing should be at least 500mVpp.

    Regards,

    Mark

  • Thanks for your reply.

    Does the differential clock described in the DATASHEET refer to other differential clocks greater than 500 mVp-p?

    Can I use the PLL chip to provide a LVPECL clock for AD9744?If I want to use PLL chip how to solve the data and clock synchronization problem?

  • Hi,

    Does the differential clock described in the DATASHEET refer to other differential clocks greater than 500 mVp-p?

    What do you mean by this? There's only one differential clock input to the DAC and it should have a minimum swing of 500mV for proper DAC operation.

    Can I use the PLL chip to provide a LVPECL clock for AD9744?If I want to use PLL chip how to solve the data and clock synchronization problem?

    Yes, you can set the clock input mode of AD9744 to PECL mode. Double check that the PLL output you want to use meets the minimum 500mV differential swing. 

    For the data and clock sync problem, make sure that the DAC clock and the clock of the FPGA (or microcontroller) that you're using to send the data into the DAC has no delay/phase difference. You may want to source both DAC and FPGA clock using one clock source.

    Regards,

    Mark

  • SNR=-20log(2πfTj),For My target output frequency the clk jitter must be lower than 2ps,so I want use PLL chip for jitter clean.would you please help me to check the below tow plan ,witch one is appropriate.

      

    I need a 100mHz clk frequency,For Plan A ,the single clk mode.Both the data and the clock are form FPGA, which can solve the synchronization problem very well. I‘m not sure whether the jitter of the FPGA output clock is less than 2ps.Tthe FPGA only output a clk such as LVDS,no one mode swing meets the minimum 500mV .So can not use the Diff mode , Single-ended clocks may pose some challenges to PCB routing.

    For plan B,use diff clk mode,The DAC clock comes from the PLL chip and can determine that the clock jitter is less than 2ps . It can also be very good anti-interference. I'm also not sure if there is a delay in the FPGA data output.

    would you give me some advice?

    Thanks!

  • Hi,

    Plan B is better since we don't recommend clocking our DACs with clock coming from FPGA since the jitter is not that good. You should be fine with that configuration. One good practice is to place the FPGA and DAC as close as you can.

    Regards,

    Mark