AD9176 inconsistent PLL lock and output

Hello,

I have a design using the AD9176-FMC-EBZ tied to an Opal Kelly eval board (so nothing custom).

My design used to work consistently when I had it setup for:
PLL ref clock = "other frequency"
PLL manual ref clock = 300MHz
link mode = dual
JESD mode = 9
channel interp = 1
datapath interp = 8
subclass = 1
input data rate = 1.2GHz
derived DAC clock rate = 9.6GHz

This seemed to be consistently good for my test design and I had no issues.

I then changed things slightly to increase my DAC clock rate:
PLL ref clock = "other frequency"
PLL manual ref clock = 250MHz
link mode = dual
JESD mode = 9
channel interp = 1
datapath interp = 12
subclass = 1
input data rate = 1GHz
derived DAC clock rate = 12GHz

And here is where my issues arise.  I used ACE to generate my register configs like I did for the previous setup.  I then incorporated them into my micoBlaze processor.  When things work, they work perfectly, but I don't see consistent results, I get a lot of unlocked PLL reads.  Once I get past that, I still have about a 1 in 4 chance of seeing any output still.  When I get the output, it is fine.  There seems to be no pattern for how many PLL unlocks I will get, nor when everything will eventually work.  I am thinking that there is something I need to do for better consistency, but I can't figure out what.

Any ideas?

Parents
  • +1
    •  Analog Employees 
    on Jan 20, 2021 7:05 PM 1 month ago

    Hello G

    By default, AD9176-FMC-EBZ uses HMC7044 to generate all JESD204B clocks (BR/40 to the FPGA, SYSREF to both FPGA and AD9176). The HMC7044 has two PLLs - PLL1 locks a 122.88MHz VCXO to an external ref, and PLL2 locks an internal VCO to the VCXO. The dual-loop allows for better jitter when using a low-quality external ref. 

    If the AD9176 PLL ref is not frequency-aligned to the HMC7044's PLL2 reference (the 122.88MHz VCXO), the BR/40 will drift relative to the AD9176 DACCLK and all its clock domains, including the SERDES PLL, and the link will be "flaky" if the various PLLs align such that they are on each other's clock boundaries. So having a common reference to all the clocks is important. 

    HMC7044 PLLs, as implemented in ACE, are integer-only. So the ref must be int-mult of 122.88MHz. 

    Easiest in ACE, is to specify datarates that are also int-mult of 122.88MHz. This way all clocks scale accordingly, and satisfy the 122.88 rate.

    You could replace the VCXO to a 100MHz or 120MHz. But ACE would still expect the 122.88MHz rate, so you may have to "hack" ACE to play nice.

    I am somewhat suprised you were able to get condition #1 working. I would not expect it to. My guess is you got lucky with the resulting rates and the relative path lengths of the clock references - but if you were to reset the link repeatedly, it could fail when the SERDES PLL in either the FPGA or the AD9176 is reset.

    I hope the explanation helps. Please let me know if condition #2 works with Fdac=12,042.24 MHz (datarate = 1,003.52 MSPS).

    one more comment. You could also provide an external BR/40. But unfortunately there is no easy way to route an external SYSREF to the AD9176. So would have to operate the link in subclass 0. Or solder a twisted pair onto the input caps, differentially, in hopes that the resulting edge will be clean enough... with careful rework it usually is. 

    Landsman

  • I was mistaken, the one set of values does meet all the criteria (I was plugging it into the Xilinx core wrong).
    If I set the PLL Ref Clock to 245.76
    Dual Link 9/1/12
    Subclass 1
    input data rate 983.04MHz
    I get a late rate of 9.8304 Gbps
    and a DAC clock rate of 11.79648 GHz

    Those values are all acceptable in the Xilinx JESD PHY core.  Unfortunately, I am still seeing inconsistent results.  I've only run it about a dozen times so far, and I don't think I've seen a DLL/PLL error, but sometimes it seems like it is outputting the data correctly, and other times I don't get anything out.  I check when I am getting no data out of the DAC, and the lights seems to be all green in ACE.  I attached the export of the registers from ACE, but nothing pops out to me as an issue.  For completeness sake, I also included the macro that ACE produces (actually I couldn't figure out how to upload them, so I had to create a Microsoft OneDrive link for them).

    https://gardettoengineering-my.sharepoint.com/:x:/p/jason/ETIi-f2NICNGtCMQDPLqa5UB8wnTSl4X61izFL5zQZfqwg?e=Z5qNb0

    https://gardettoengineering-my.sharepoint.com/:u:/p/jason/EWhuqFm9O_RKktPlHhWbDKsBusB1lOmUiT_nKUKXyx5LZg?e=G8e7Hg

Reply Children
No Data