AD9102 SRAM Read/Write

Hi,


Please see pseudocode below.

1. Set initial values of IOs.
     ○ RESET - logic high
     ○ TRIGGER - logic high
     ○ CS - logic high

2. Set SPI frequency and mode.
     ○ Clock is logic low when idle or leads with a rising edge and trails with a falling edge.
     ○ Data logic level should be valid during the clock rising edge and before the clock falling edge.

3. Pulse RESET to logic low then high to reset register values.

4. Proceed with register read or write. (AD9102: page 18, AD9106: pages 22-23 of datasheet)
     a. If loading a pattern from SRAM, write data on SRAM registers first. (AD9102: page 23, AD9106: page 27 of datasheet)
          i. To write data: Enable MEM_ACCESS bit in 0x1E register. Write left-justified data to SRAM registers, 0x6000 to 0x6FFF. Disable MEM_ACCESS bit.
          ii. To read data: Enable BUF_READ and MEM_ACCESS bits in 0x1E register. After reading data from SRAM registers, disable BUF_READ and MEM_ACCESS bits.
     b. Write on SPI registers. Update last bits of registers 0x1E (RUN bit) and 0x1D (RAMUPDATE bit) at the end of the write sequence.


Best regards,
Shine

Hello Shine, thank you for the assistance.

Following these steps, I am still unable to write and then read to the SRAM.

1. State of I/Os: RESET_B is HIGH (+3.325V); TRIGGER_B is LOW (+0.001V); CSB is HIGH (+3.341V)
   1. Verified with a calibrated multimeter probing the actual dev board
2. SPI Frequency and Mode
   1. Frequency is 714kHz (1.4us)
   2. CS is Active Low
   3. Clock is Rising Edge
3. Pulse Reset Low then High
   1. I press and hold S1 for ~1second
4. Write SRAM Data
   1. Read PAT_STATUS = 0x0000 (Checking for RUN Bit)
   2. Read PAT_STATUS = 0x0000 (Getting Current Register Status)
   3. Write PAT_STATUS MEM_ACCESS = 0x001E 0x0004
   4. Write RAM_UPDATE UPDATE = 0x001D 0x0001
   5. Write SRAM DATA = 0x6000 0x0000 0xAAB0 0x5560 0x0010
   6. Read PAT_STATUS = 0x0004 (Checking for RUN Bit)
   7. Read PAT_STATUS = 0x0004 (Getting Current Register Status)
   8. Write PAT_STATUS = 0x001E 0x0000
5. Read SRAM Data
   1. Read PAT_STATUS = 0x0000 (Checking for RUN Bit)
   2. Read PAT_STATUS = 0x0000 (Getting Current Register Status)
   3. Write PAT_STATUS BUF_READ and MEM_ACCESS = 0x001E 0x000C
   4. Write RAM_UPDATE UPDATE = 0x001D 0x0001
   5. Read SRAM DATA =
      1. MOSI: 0xE000 0x0000 0x0000 0x0000 0x0000
      2. MISO: 0x0000 0x0000 0x0000 0x0000 0x0000
         1. MISO Should be 0x0000 0x0000 0xAAB0 0x5560 0x0010
   6. Read PAT_STATUS = 0x000C (Checking for RUN Bit)
   7. Read PAT_STATUS = 0x000C (Getting Current Register Status)
   8. Write PAT_STATUS = 0x001E 0x0000

If it is helpful, I can provide CVS files that show the exact timing of the signals.

Hi Chad,

Were you able to successfully write data to and read from the SRAM?

Best regards,
Shine

Hello,

Yes, I was finally able to get get the read/write to the SRAM after a lot of experimentation.  I ended up having to re-write my functions to Write the data in reverse (because the counter decrements) and to Read the SRAM data 16-bits at a time (because the counter does not change).

Do you know if they are planning to release an updated datasheet that fixes all of the typos and misinformation?

Hi Chad,

There is a plan, yes. But we'll be prioritizing creation of new eval board user guide with updated information on the SPI interface.

Thank you for the recommendation.

Best regards,
Shine

Hi Chad,

There is a plan, yes. But we'll be prioritizing creation of new eval board user guide with updated information on the SPI interface.

Thank you for the recommendation.

Best regards,
Shine

hello shineC,

please can you tell me proper procedure for write and read sram data. and values for set sram mode in registers.... and what is reading address of sram. 

Hello,

Please refer to this page https://wiki.analog.com/resources/eval/dpg/eval-ad9106

Regards,
Shine